Patents by Inventor Dung Q. Nguyen

Dung Q. Nguyen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200201646
    Abstract: Techniques for parallel execution of instructions in an instruction set are described. The techniques include determining a plurality of instruction streams and paths for a branch in an instruction set and executing the determined paths in parallel such that a mis-predicted path does not cause significant mis-prediction penalties.
    Type: Application
    Filed: December 20, 2018
    Publication date: June 25, 2020
    Inventors: Brian W. THOMPTO, Hung Q. LE, Dung Q. NGUYEN
  • Publication number: 20200201639
    Abstract: A computer system includes a dispatch routing network to dispatch a plurality of instructions, and a processor in signal communication with the dispatch routing network. The processor determines a move instruction from the plurality of instructions to move data produced by an older second instruction, and copies a splice target file (STF) tag from a source register of the move instruction to a destination register of the move instruction without physically copying data in a slice target register and without assigning a new STF tag destination to the move instruction.
    Type: Application
    Filed: December 20, 2018
    Publication date: June 25, 2020
    Inventors: Joshua Bowman, Dung Q. Nguyen, Hung Le, Brian Thompto, Maureen A. Delaney, Cliff Kucharski, Steven J Battle
  • Publication number: 20200183701
    Abstract: A computer system, processor, and method for processing information is disclosed that includes reading out a plurality of entries in a history buffer prior to initiating a flush recovery process; initiating the flush recovery process; determining which of the history buffer entries read out of the history buffer should be recovered; and sending information associated with the history buffer entries to be recovered to one or more history buffer recovery ports. In one or more embodiments, the history buffer entries are continually read out in response to a processor and history buffer entries read out from the history buffer are directed to a specific history buffer recovery port associated with a mapper of a specific logical register.
    Type: Application
    Filed: December 5, 2018
    Publication date: June 11, 2020
    Inventors: Steven J. Battle, Khandker Nabil Adeeb, Brian D. Barrick, Joshua W. Bowman, Susan E. Eisen, Brandon Goddard, Jamory Hawkins, Dung Q. Nguyen
  • Publication number: 20200183700
    Abstract: A computer system, processor, and method for processing information is disclosed that includes partitioning a logical register in the processor into a plurality of ranges of logical register entries based upon the logical register entry, assigning at least one recovery port of a history buffer to each range of logical register entries, initiating a flush recovery process for the processor, and directing history buffer entries to the assigned recovery port based upon the logical register entry associated with the history buffer entry.
    Type: Application
    Filed: December 5, 2018
    Publication date: June 11, 2020
    Inventors: Steven J. Battle, Salma Ayub, Brian D. Barrick, Joshua W. Bowman, Susan E. Eisen, Brandon Goddard, Christopher M. Mueller, Dung Q. Nguyen
  • Publication number: 20200167166
    Abstract: A computing system includes an issue queue and a microprocessor. The issue queue receives a fused instruction, which includes a first instruction portion fused with a second instruction portion different from the first instruction portion. The microprocessor assigns a first instruction tag (ITAG) to the first instruction portion and a second ITAG to the second instruction portion. The microprocessor determines a first bit that represents the first ITAG, inverts the first bit to determine a second bit that represents the second ITAT, and determines an availability of one or more sources of a second instruction different from the fused instruction based at least in part on the first bit or the second bit.
    Type: Application
    Filed: November 28, 2018
    Publication date: May 28, 2020
    Inventors: Michael J. Genden, Hung Q. Le, Dung Q. Nguyen, Brian W. Thompto
  • Patent number: 10664275
    Abstract: Mechanisms are provided, in a processor, for executing instructions that are younger than a previously dispatched synchronization (sync) instruction is provided. An instruction sequencer unit of the processor dispatches a sync instruction. The sync instruction is sent to a nest of one or more devices outside of the processor. The instruction sequencer unit dispatches a subsequent instruction after dispatching the sync instruction. The dispatching of the subsequent instruction after dispatching the sync instruction is performed prior to receiving a sync acknowledgement response from the nest. The instruction sequencer unit performs a completion of the subsequent instruction based on whether completion of the subsequent instruction is dependent upon receiving the sync acknowledgement from the nest and completion of the sync instruction.
    Type: Grant
    Filed: August 30, 2018
    Date of Patent: May 26, 2020
    Assignee: International Business Machines Corporation
    Inventors: Susan E. Eisen, Hung Q. Le, Bryan J. Lloyd, Dung Q. Nguyen, David S. Ray, Benjamin W. Stolt, Shih-Hsiung S. Tung
  • Publication number: 20200159564
    Abstract: A computer system, processor, and method for processing information is disclosed that includes at least one computer processor for processing instructions, the processor having a history buffer having a plurality of entries for storing information associated with a processor instruction evicted from a logical register, the history buffer having a at least one recovery port; a logical register mapper for recovering information from the history buffer, the mapper having restore ports to recover information from the history buffer; and a restore multiplexor configured to receive as inputs information from one or more of the history buffer recovery ports, and configured to output information to one or more of the logical register mapper restore ports. The processor, system and/or method configured to improve flush recovery bandwidth.
    Type: Application
    Filed: November 16, 2018
    Publication date: May 21, 2020
    Inventors: Steven J. Battle, Khandker Nabil Adeeb, Brian D. Barrick, Joshua W. Bowman, Susan E. Eisen, Brandon Goddard, Jamory Hawkins, Dung Q. Nguyen
  • Patent number: 10649779
    Abstract: Techniques disclosed herein describe a variable latency pipe for interleaving instruction tags in a processor. According to one embodiment presented herein, an instruction tag is associated with an instruction upon issue of the instruction from the issue queue. One of a plurality of positions in the latency pipe is determined. The pipe stores one or more instruction tags, each associated with a respective instruction. The pipe also stores the instruction tags in a respective position based on the latency of each respective instruction. The instruction tag is stored at the determined position in the pipe.
    Type: Grant
    Filed: March 17, 2016
    Date of Patent: May 12, 2020
    Assignee: International Business Machines Corporation
    Inventors: Salma Ayub, Josh Bowman, Sundeep Chadha, Dhivya Jeganathan, Cliff Kucharski, Dung Q. Nguyen
  • Publication number: 20200142697
    Abstract: A computer-implemented method, computer program product, and computer processing system are provided. The method includes processing, by a superscalar processing pipeline, respective sets of instructions in respective instruction processing cycles using an Instruction Completion Table (ICT) with a Ready-To-Complete (RTC) vector. The ICT includes a plurality of entries, each corresponding to a respective one of the instructions. A Next-To-Complete (NTC) instruction from among the respective sets of instructions is computed using the RTC vector.
    Type: Application
    Filed: November 7, 2018
    Publication date: May 7, 2020
    Inventors: Kenneth L. Ward, Susan E. Eisen, Glenn O. Kincaid, Dung Q. Nguyen, Deepak K. Singh, Gaurav Mittal, Christopher M. Mueller
  • Patent number: 10635444
    Abstract: An apparatus for shared compare lanes for dependency wakeup in a double issue queue includes a source dependency module that determines a number of source dependencies for two instructions to be paired in a row of a double issue queue of a processor. A source dependency includes an unavailable status of a dependent source for data required by the two instructions where the data is produced by another instruction. The apparatus includes a pairing determination module that writes each of the two instructions into a separate row of the double issue queue in response to the source dependency module determining that the number of source dependencies is greater than a source dependency maximum and pairs the two instructions in one row of the double issue queue in response to the source dependency module determining that the number of source dependencies is less than or equal to the source dependency maximum.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: April 28, 2020
    Assignee: INTERNATIONAL BUSINSS MACHINES CORPORATION
    Inventors: Michael J. Genden, Dung Q. Nguyen, Hung Q. Le, Brian W. Thomto
  • Patent number: 10613868
    Abstract: Techniques disclosed herein describe a variable latency pipe for interleaving instruction tags in a processor. According to one embodiment presented herein, an instruction tag is associated with an instruction upon issue of the instruction from the issue queue. One of a plurality of positions in the latency pipe is determined. The pipe stores one or more instruction tags, each associated with a respective instruction. The pipe also stores the instruction tags in a respective position based on the latency of each respective instruction. The instruction tag is stored at the determined position in the pipe.
    Type: Grant
    Filed: June 30, 2015
    Date of Patent: April 7, 2020
    Assignee: International Business Machines Corporation
    Inventors: Salma Ayub, Josh Bowman, Sundeep Chadha, Dhivya Jeganathan, Cliff Kucharski, Dung Q. Nguyen
  • Patent number: 10592422
    Abstract: A microprocessor has a data-less history buffer. Operands associated with a program instructions are stored in logical registers (LREGs) which are resolvable to physical registers that are not part of the history buffer. Register re-naming maintains integrity of data dependencies for instructions processed out of program order. The history buffer has pointers (RTAGs) to the LREGs. Entries in the history buffer are grouped into ranges. A mapper has a single port associated with each LREG, and each port receives data, from a single range of entries in the history buffer. Multiple entries, one from each range, may be restored concurrently from the history buffer to the mapper.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: March 17, 2020
    Assignee: International Business Machines Corporation
    Inventors: Brian D. Barrick, Gregory W. Alexander, Dung Q. Nguyen
  • Publication number: 20200081713
    Abstract: An approach is provided in which a system writes a set of data into a register file entry that includes a first memory array and a second memory array. The register file entry also includes a set of first write ports corresponding to the first memory array and a set of second write ports corresponding to the second memory array. The system configures a selection bit based on determining that a selected one of the set of first write ports is utilized to store the set of data in the first memory array. In turn, the system reads the set of data out of the first memory array based on the configured selection bit.
    Type: Application
    Filed: September 6, 2018
    Publication date: March 12, 2020
    Inventors: Saiful Islam, Sam G. Chu, Dung Q. Nguyen, Binglong Zhang, Howard Levy, David R. Terry, Steven J. Battle
  • Publication number: 20200073668
    Abstract: Embodiments of the present invention provide systems and methods for mapping the architected state of one or more threads to a set of distributed physical register files to enable independent execution of one or more threads in a multiple slice processor. In one embodiment, a system is disclosed including a plurality of dispatch queues which receive instructions from one or more threads and an even number of parallel execution slices, each parallel execution slice containing a register file. A routing network directs an output from the dispatch queues to the parallel execution slices and the parallel execution slices independently execute the one or more threads.
    Type: Application
    Filed: November 7, 2019
    Publication date: March 5, 2020
    Inventors: Sam G. Chu, Markus Kaltenbach, Hung Q. Le, Jentje Leenstra, Jose E. Moreira, Dung Q. Nguyen, Brian W. Thompto
  • Publication number: 20200065102
    Abstract: Method and apparatus for a completion mechanism for a microprocessor are provided by marking entries in a section of an Instruction Completion Table (ICT) as ready to complete using corresponding Ready to Complete (RTC) status bits; determining a tail pointer indicating a start of the entries in the ICT that are ready for completion in a current clock cycle; performing a counting leading ones on an RTC vector that organizes the RTC status bits according to a program order for completing the entries to determine a count leading ones pointer that indicates an end of the entries in the ICT that are ready for completion in the current clock cycle; completing instructions included in the entries between the tail pointer and the count leading ones pointer in one clock cycle; and updating the tail pointer to a value of the count leading ones pointer for a subsequent clock cycle.
    Type: Application
    Filed: August 23, 2018
    Publication date: February 27, 2020
    Inventors: Kenneth L. WARD, Susan E. EISEN, Dung Q. NGUYEN, Glenn O. KINCAID, Joe LEE, Deepak K. SINGH
  • Publication number: 20200065110
    Abstract: Method and apparatus for stopping completions using stop codes in an instruction completion table are provided by during a first clock cycle, in response to determining that a given entry in an Instruction Completion Table (ICT) is finalized and is associated with a stop code, completing, according to a program order, instructions included in one or more finalized entries of the ICT located in the ICT before the given entry; during a second clock cycle, after completing the instructions, performing exception processing for a special instruction included in the given entry; and during a third clock cycle, after processing the special instruction, completing, according to the program order, additional instructions in one or more finalized entries located in the ICT after the given entry.
    Type: Application
    Filed: August 23, 2018
    Publication date: February 27, 2020
    Inventors: Kenneth L. WARD, Dung Q. NGUYEN, Susan E. EISEN, Christopher M. MUELLER, Joe LEE, Deepak K. SINGH
  • Publication number: 20200065103
    Abstract: Method and apparatus for completing atomic instructions in a microprocessor may be provided by identifying from a program-ordered Instruction Completion Table (ICT) a last entry in a completion window of instructions for completion in a current clock cycle of a processor; in response to determining that the last entry includes an atomic instruction that straddles the completion window: excluding the last entry from completion during the current clock cycle; completing instructions in the completion window for the current clock cycle; and shifting the completion window to include the last entry and a next entry adjacent to the last entry in the ICT in a next clock cycle.
    Type: Application
    Filed: August 23, 2018
    Publication date: February 27, 2020
    Inventors: Kenneth L. WARD, Susan E. EISEN, Dung Q. NGUYEN, Glenn O. KINCAID, Joe LEE, Deepak K. SINGH
  • Patent number: 10564691
    Abstract: Reducing power consumption in a multi-slice computer processor that includes a re-order buffer and an architected register file, including: designating an entry in the re-order buffer as being invalid and unwritten; assigning a pending instruction to the entry in the re-order buffer; responsive to assigning the pending instruction to the entry in the re-order buffer, designating the entry as being valid; writing data generated by executing the pending instruction into the re-order buffer; and responsive to writing data generated by executing the pending instruction into the re-order buffer, designating the entry as being written.
    Type: Grant
    Filed: November 3, 2017
    Date of Patent: February 18, 2020
    Assignee: International Business Machines Corporation
    Inventors: Steven J. Battle, Owen Chiang, Sam G. Chu, Saiful Islam, Dung Q. Nguyen, David R. Terry, Eula A. Tolentino
  • Publication number: 20200042319
    Abstract: A computer system, processor, and method for processing information is disclosed that includes a Dispatch Unit for dispatching instructions; an Issue Queue for receiving instructions dispatched from the Dispatch Unit; and a queue for receiving instructions issued from the Issue Queue, the queue having a plurality of entry locations for storing data. In an embodiment instructions are dispatched with a virtual indicator, and the virtual indicator is set to a first mode for instructions dispatched where an entry location is available, and to a second mode where an entry location is not available, in the queue to receive the dispatched instruction. In addition to virtual tagging dispatched instructions, a system, processor, and method are disclosed for regional partitioning of queues, region based deallocation of queue entries, and circular thread based assignment of queue entries.
    Type: Application
    Filed: August 2, 2018
    Publication date: February 6, 2020
    Inventors: Bryan Lloyd, Brian D. Barrick, Kurt A. Feiste, Hung Q. Le, Dung Q. Nguyen, Kenneth L. Ward
  • Publication number: 20200042321
    Abstract: An apparatus for back-to-back wakeup and issue of paired instructions is disclosed includes a paired dependency module that identifies that a dependent source of a younger instruction is a result of an older instruction. The older instruction and the younger instruction include paired instructions in a double issue queue of a processor. The apparatus includes a wakeup bit circuit that sets a wakeup bit corresponding to the dependent source of the younger instruction that is dependent on the results of the older instruction in response to the paired dependency module identifying that a dependent source of the younger instruction is a result of the older instruction and the older instruction being issued. The wakeup bit circuit sets the wakeup bit in a same clock cycle as the older instruction issues.
    Type: Application
    Filed: July 31, 2018
    Publication date: February 6, 2020
    Inventors: Michael J. Genden, Hung Q. Le, Dung Q. Nguyen, Brian W. Thompto