Patents by Inventor Dung V. Nguyen
Dung V. Nguyen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11960722Abstract: A memory device includes an array of memory cells and a controller configured to access the array of memory cells. The controller is further configured to program a first number of bits to a first memory cell of the array of memory cells and program a second number of bits to a second memory cell of the array of memory cells. The controller is further configured to following a period after programming the second number of bits to the second memory cell, merge at least a subset of the first number of bits stored in the first memory cell to the second number of bits stored in the second memory cell without erasing the second memory cell such that the second number of bits plus at least the subset of the first number of bits are stored in the second memory cell.Type: GrantFiled: July 25, 2022Date of Patent: April 16, 2024Assignee: Micron Technology, Inc.Inventors: Tomoharu Tanaka, Huai-Yuan Tseng, Dung V. Nguyen, Kishore Kumar Muchherla, Eric N. Lee, Akira Goda, James Fitzpatrick, Dave Ebsen
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Publication number: 20240094942Abstract: A request to perform a data operation associated with at least one memory unit in a plurality of memory units of a memory device is received. The at least one memory unit includes a first group of memory cells, each memory cell supporting a specified number of charge levels such that each memory cell having the specified charge level represents a non-integer number of bits. The first group of memory cells represents a first sequence of bits based on a first sequence of charge levels formed by the first group of memory cells. The data operation is performed with respect to the at least one memory unit based on a mapping stored on the system. The mapping assigns an individual sequence of charge levels from an individual group cell to an individual sequence of bits represented by the individual group of memory cells.Type: ApplicationFiled: November 28, 2023Publication date: March 21, 2024Inventor: Dung V. Nguyen
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Publication number: 20240087651Abstract: Exemplary methods, apparatuses, and systems include an adaptive pre-read manager for controlling pre-reads of the memory device. The adaptive pre-read manager receives a first set of data bits for programming to memory. The adaptive pre-read manager performing a first pass of programming including a first subset of data bits from the set of data bits. The adaptive pre-read manager compares a set of threshold operating differences to a set of differences between multiple operating conditions during the first pass of programming and current operating conditions. The adaptive pre-read manager performs an internal pre-read of the programmed first subset of data bits. The adaptive pre-read manager performs a second pass of programming using the internal pre-read and a second subset of data bits from the first set of data bits.Type: ApplicationFiled: September 9, 2022Publication date: March 14, 2024Inventors: Kishore Kumar Muchherla, Huai-Yuan Tseng, Akira Goda, Dung V. Nguyen, Giovanni Maria Paolucci, James Fitzpatrick, Eric N. Lee, Dave Scott Ebsen, Tomoharu Tanaka
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Publication number: 20240062799Abstract: Methods, apparatuses and systems related to maintaining stored data are described. The apparatus may be configured to refresh the stored data according to schedule that includes different delays between successive refresh operations.Type: ApplicationFiled: August 17, 2022Publication date: February 22, 2024Inventors: Huai-Yuan Tseng, Akira Goda, Kishore Kumar Muchherla, James Fitzpatrick, Tomoharu Tanaka, Eric N. Lee, Dung V. Nguyen, David Ebsen
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Publication number: 20240028200Abstract: A memory device includes an array of memory cells and a controller configured to access the array of memory cells. The controller is further configured to program a first number of bits to a first memory cell of the array of memory cells and program a second number of bits to a second memory cell of the array of memory cells. The controller is further configured to following a period after programming the second number of bits to the second memory cell, merge at least a subset of the first number of bits stored in the first memory cell to the second number of bits stored in the second memory cell without erasing the second memory cell such that the second number of bits plus at least the subset of the first number of bits are stored in the second memory cell.Type: ApplicationFiled: July 25, 2022Publication date: January 25, 2024Applicant: MICRON TECHNOLOGY, INC.Inventors: Tomoharu Tanaka, Huai-Yuan Tseng, Dung V. Nguyen, Kishore Kumar Muchherla, Eric N. Lee, Akira Goda, James Fitzpatrick, Dave Ebsen
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Publication number: 20240028252Abstract: Exemplary methods, apparatuses, and systems include a quick charge loss (QCL) mitigation manager for controlling writing data bits to a memory device. The QCL mitigation manager receives a first set of data bits for programming to memory. The QCL mitigation manager writes a first subset of data bits of the first set of data bits to a first memory block of the memory during a first pass of programming. The QCL mitigation manager writes a second subset of data bits of the first set of data bits to the first memory block during a second pass of programming in response to determining that the threshold delay is satisfied.Type: ApplicationFiled: July 25, 2022Publication date: January 25, 2024Inventors: Kishore Kumar Muchherla, Dung V. Nguyen, Dave Scott Ebsen, Tomoharu Tanaka, James Fitzpatrick, Huai-Yuan Tseng, Akira Goda, Eric N. Lee
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Patent number: 11869595Abstract: A command to program data to a memory device is received. Target charge levels of a set of memory cells in the memory device for a first programming step are determined based on the data. A first set of indicators are provided to the memory device. The first set of indicators indicate the target charge levels for the first programming step. Target charge levels of the set of memory cells for a second programming step are determined based on the data. A second set of indicators are provided to the memory device. The second set of indicators indicate the target charge levels for the second programming step.Type: GrantFiled: December 20, 2022Date of Patent: January 9, 2024Assignee: Micron Technology, Inc.Inventors: Dung V. Nguyen, Phong Sy Nguyen
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Patent number: 11861208Abstract: A request to perform a data operation associated with at least one memory unit in a plurality of memory units of a memory device is received. The at least one memory unit includes a first group of memory cells, each memory cell supporting a specified number of charge levels such that each memory cell having the specified charge level represents a non-integer number of bits. The first group of memory cells represents a first sequence of bits based on a first sequence of charge levels formed by the first group of memory cells. The data operation is performed with respect to the at least one memory unit based on a mapping stored on the system. The mapping assigns an individual sequence of charge levels from an individual group cell to an individual sequence of bits represented by the individual group of memory cells.Type: GrantFiled: December 22, 2020Date of Patent: January 2, 2024Assignee: Micron Technology, Inc.Inventor: Dung V. Nguyen
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Patent number: 11663079Abstract: Exemplary methods, apparatuses, and systems include receiving a request for a segment of data. The requested segment data is one of a plurality of segments of data in a stripe of data. A failure to decode the requested segment is detected. Each of the plurality of segments in the stripe other than the requested segment are read. Reading each segment includes reading raw encoded data and attempting to decode the raw encoded data, the result of reading each segment including decoded data when decoding is successful and the raw encoded data when decoding fails. A combined result of each read is generated. The combining includes combining decoded data for segments that were successfully decoded and the raw encoded data for segments for which decoding failed. A statistical model for the requested segment is updated using the combined result. The requested segment is decoded using the updated statistical model.Type: GrantFiled: December 1, 2021Date of Patent: May 30, 2023Assignee: MICRON TECHNOLOGY, INC.Inventors: Dung V. Nguyen, Phong Sy Nguyen, Sivagnanam Parthasarathy
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Publication number: 20230121705Abstract: A command to program data to a memory device is received. Target charge levels of a set of memory cells in the memory device for a first programming step are determined based on the data. A first set of indicators are provided to the memory device. The first set of indicators indicate the target charge levels for the first programming step. Target charge levels of the set of memory cells for a second programming step are determined based on the data. A second set of indicators are provided to the memory device. The second set of indicators indicate the target charge levels for the second programming step.Type: ApplicationFiled: December 20, 2022Publication date: April 20, 2023Inventors: Dung V. Nguyen, Phone Sy Nguyen
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Patent number: 11568937Abstract: A command to program data to a memory device is received. Target charge levels of a set of memory cells in the memory device for a first programming step are determined based on the data. A first set of indicators are provided to the memory device. The first set of indicators indicate the target charge levels for the first programming step. Target charge levels of the set of memory cells for a second programming step are determined based on the data. A second set of indicators are provided to the memory device. The second set of indicators indicate the target charge levels for the second programming step.Type: GrantFiled: March 29, 2021Date of Patent: January 31, 2023Assignee: Micron Technology, Inc.Inventors: Dung V. Nguyen, Phong Sy Nguyen
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Patent number: 11562776Abstract: A request to perform a read operation on a memory device is received. The memory device includes a first group of memory cells. The first group of memory cells represents a first sequence of bits based on a first sequence of charge levels formed by the first group of memory cells. The read operation is performed by obtaining a first read signal for a first memory cell and a second read signal for a second memory cell of the first group of memory cells. A first rule logic is applied to the first read signal to generate a first updated signal and a second rule logic is applied to the second read signal to generate a second updated signal. Logic functions are applied to the first and second updated signals to generate an output signal indicating the first sequence of bits stored by the first group of memory cells.Type: GrantFiled: June 8, 2021Date of Patent: January 24, 2023Assignee: Micron Technology, Inc.Inventor: Dung V. Nguyen
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Publication number: 20220392500Abstract: A request to perform a read operation on a memory device is received. The memory device includes a first group of memory cells. The first group of memory cells represents a first sequence of bits based on a first sequence of charge levels formed by the first group of memory cells. The read operation is performed by obtaining a first read signal for a first memory cell and a second read signal for a second memory cell of the first group of memory cells. A first rule logic is applied to the first read signal to generate a first updated signal and a second rule logic is applied to the second read signal to generate a second updated signal. Logic functions are applied to the first and second updated signals to generate an output signal indicating the first sequence of bits stored by the first group of memory cells.Type: ApplicationFiled: June 8, 2021Publication date: December 8, 2022Inventor: Dung V. Nguyen
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Publication number: 20220310164Abstract: A command to program data to a memory device is received. Target charge levels of a set of memory cells in the memory device for a first programming step are determined based on the data. A first set of indicators are provided to the memory device. The first set of indicators indicate the target charge levels for the first programming step. Target charge levels of the set of memory cells for a second programming step are determined based on the data. A second set of indicators are provided to the memory device. The second set of indicators indicate the target charge levels for the second programming step.Type: ApplicationFiled: March 29, 2021Publication date: September 29, 2022Inventors: Dung V. Nguyen, Phong Sy Nguyen
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Publication number: 20220253354Abstract: Exemplary methods, apparatuses, and systems include receiving a request for a segment of data. The requested segment data is one of a plurality of segments of data in a stripe of data. A failure to decode the requested segment is detected. Each of the plurality of segments in the stripe other than the requested segment are read. Reading each segment includes reading raw encoded data and attempting to decode the raw encoded data, the result of reading each segment including decoded data when decoding is successful and the raw encoded data when decoding fails. A combined result of each read is generated. The combining includes combining decoded data for segments that were successfully decoded and the raw encoded data for segments for which decoding failed. A statistical model for the requested segment is updated using the combined result. The requested segment is decoded using the updated statistical model.Type: ApplicationFiled: December 1, 2021Publication date: August 11, 2022Inventors: Dung V. Nguyen, Phong Sy Nguyen, Sivagnanam Parthasarathy
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Publication number: 20220197538Abstract: A request to perform a data operation associated with at least one memory unit in a plurality of memory units of a memory device is received. The at least one memory unit includes a first group of memory cells, each memory cell supporting a specified number of charge levels such that each memory cell having the specified charge level represents a non-integer number of bits. The first group of memory cells represents a first sequence of bits based on a first sequence of charge levels formed by the first group of memory cells. The data operation is performed with respect to the at least one memory unit based on a mapping stored on the system. The mapping assigns an individual sequence of charge levels from an individual group cell to an individual sequence of bits represented by the individual group of memory cells.Type: ApplicationFiled: December 22, 2020Publication date: June 23, 2022Inventor: Dung V. Nguyen