Patents by Inventor Dung-Yian Hsieh

Dung-Yian Hsieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8452439
    Abstract: A method comprises computing respective regression models for each of a plurality of failure bins based on a plurality of failures identified during wafer electrical tests. Each regression model outputs a wafer yield measure as a function of a plurality of device performance variables. For each failure bin, sensitivity of the wafer yield measure to each of the plurality of device performance variables is determined, and the device performance variables are ranked with respect to sensitivity of the wafer yield measure. A subset of the device performance variables which have highest rankings and which have less than a threshold correlation with each other are selected. The wafer yield measures for each failure bin corresponding to one of the selected subset of device performance variables are combined, to provide a combined wafer yield measure. At least one new process parameter value is selected to effect a change in the one device performance variable, based on the combined wafer yield measure.
    Type: Grant
    Filed: March 15, 2011
    Date of Patent: May 28, 2013
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Sunny Wu, Chun-Hsien Lin, Kun-Ming Chen, Dung-Yian Hsieh, Hui-Ru Lin, Jo Fei Wang, Jong-I Mou, I-Ching Chu
  • Publication number: 20120239178
    Abstract: A method comprises computing respective regression models for each of a plurality of failure bins based on a plurality of failures identified during wafer electrical tests. Each regression model outputs a wafer yield measure as a function of a plurality of device performance variables. For each failure bin, sensitivity of the wafer yield measure to each of the plurality of device performance variables is determined, and the device performance variables are ranked with respect to sensitivity of the wafer yield measure. A subset of the device performance variables which have highest rankings and which have less than a threshold correlation with each other are selected. The wafer yield measures for each failure bin corresponding to one of the selected subset of device performance variables are combined, to provide a combined wafer yield measure. At least one new process parameter value is selected to effect a change in the one device performance variable, based on the combined wafer yield measure.
    Type: Application
    Filed: March 15, 2011
    Publication date: September 20, 2012
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Sunny Wu, Chun-Hsien Lin, Kun-Ming Chen, Dung-Yian Hsieh, Hui-Ru Lin, Jo Fei Wang, Jong-I Mou, I-Ching Chu