Abstract: A cooling cigarette filter and a smoking product are provided. The cooling cigarette filter comprises a cooling section. The cooling section is provided with one or more channels connecting two ends of the cooling section, and an inner surface of each channel is coated with a cooling material. The cooling material comprises an inorganic phase change material and PEG, and the inorganic phase change material comprises at least one of Na2CO3.10H2O, CH3COONa.3H2O, CaCl2.4H2O, and Na2SO4.10H2O. The cooling cigarette filter has the advantages of ensuring the amount of smoke and lowering the temperature of the smoke entering the mouth, especially in the cooling section. Through the combination design of the structure of the cooling stick and the type and amount of the cooling material, the smoke can flow out of a smoke generation section rapidly and smoothly.

Abstract: A cooling cigarette filter and a cigarette are disclosed. The cooling cigarette filter comprises a cooling section (2). The cooling section (2) comprises a cooling stick (201) formed from paper (5). The cooling stick (201) has one or more holes (202) communicating two ends of the cooling stick. And the surface of the paper (5) is coated with a cooling material. The cooling cigarette filter has the advantages of ensuring the amount of smoke and lowering the temperature of the smoke entering the mouth. Through the combination design of the structure of the cooling stick and the type and amount of the cooling material, the smoke can flow out of a smoke generation section rapidly and smoothly And the temperature of the high-temperature smoke before entering the mouth can be significantly lowered, thereby improving the comfort and satisfaction of smoking.

Abstract: A method for enhancing a chip layout may include obtaining the chip layout including a first layer including first and second tracks, a first route occupying the first track, and an open net including open terminals. The method may further include grouping the open terminals into at least a first subset of open terminals, calculating, based on the first subset, a region of interest (ROI), determining that neither the first track nor the second track within the ROI can be used to connect all the open terminals in the first subset, determining that the first track can be used to connect all the open terminals in the first subset after moving the first route from the first track to the second track, moving, the first route from the first track to the second track, and attempting to connect all the open terminals in the first subset using the first track.

Abstract: A method for enhancing a chip layout may include obtaining the chip layout including a first layer including first and second tracks, a first route occupying the first track, and an open net including open terminals. The method may further include grouping the open terminals into at least a first subset of open terminals, calculating, based on the first subset, a region of interest (ROI), determining that neither the first track nor the second track within the ROI can be used to connect all the open terminals in the first subset, determining that the first track can be used to connect all the open terminals in the first subset after moving the first route from the first track to the second track, moving, the first route from the first track to the second track, and attempting to connect all the open terminals in the first subset using the first track.

Abstract: A method for enhancing a chip layout may include obtaining the chip layout including a first layer including first and second tracks, a first route occupying the first track, and an open net including open terminals. The method may further include grouping the open terminals into at least a first subset of open terminals, calculating, based on the first subset, a region of interest (ROI), determining that neither the first track nor the second track within the ROI can be used to connect all the open terminals in the first subset, determining that the first track can be used to connect all the open terminals in the first subset after moving the first route from the first track to the second track, moving, the first route from the first track to the second track, and attempting to connect all the open terminals in the first subset using the first track.

Abstract: A method for enhancing a chip layout may include obtaining the chip layout including a first layer including first and second tracks, a first route occupying the first track, and an open net including open terminals. The method may further include grouping the open terminals into at least a first subset of open terminals, calculating, based on the first subset, a region of interest (ROI), determining that neither the first track nor the second track within the ROI can be used to connect all the open terminals in the first subset, determining that the first track can be used to connect all the open terminals in the first subset after moving the first route from the first track to the second track, moving, the first route from the first track to the second track, and attempting to connect all the open terminals in the first subset using the first track.

Abstract: Systems, methods, and other embodiments associated with providing obstacle-avoidance bus routing for an integrated circuit design are described. In one embodiment, a bus routing tool is disclosed that generates a plurality of escape nodes to construct a three-dimensional routing solution graph. The bus routing tool probes a design space of the integrated circuit design to dynamically determine a location of each escape node while avoiding path blockages within the design space. By traversing the three-dimensional routing solution graph from a leaf escape node near a target location within the design space back to a root escape node near a source location within the design space, a candidate routing solution for routing a signal bus from the source location to the target location can be determined.

Abstract: A method for manipulating a circuit design includes receiving multiple dummy cell modification parameters, selecting, by a computer processor and based on the dummy cell modification parameters, a dummy cell insertion region on a circuit design, and generating, in the dummy cell insertion region, multiple dummy cells. The method further includes selecting a first dummy cell from the dummy cells, determining, by the computer processor and based on a location of the first dummy cell, an illegal overlap with the first dummy cell, and removing, by the computer processor and from the dummy cells, the first dummy cell. The method further includes inserting, by the computer processor, on the circuit design, and after removing the first dummy cell, the dummy cells to obtain a modified circuit design, and presenting the modified circuit design.

Abstract: Systems, methods, and other embodiments associated with providing obstacle-avoidance bus routing for an integrated circuit design are described. In one embodiment, a bus routing tool is disclosed that generates a plurality of escape nodes to construct a three-dimensional routing solution graph. The bus routing tool probes a design space of the integrated circuit design to dynamically determine a location of each escape node while avoiding path blockages within the design space. By traversing the three-dimensional routing solution graph from a leaf escape node near a target location within the design space back to a root escape node near a source location within the design space, a candidate routing solution for routing a signal bus from the source location to the target location may be determined.

Abstract: A method for manipulating a circuit design includes receiving multiple dummy cell modification parameters, selecting, by a computer processor and based on the dummy cell modification parameters, a dummy cell insertion region on a circuit design, and generating, in the dummy cell insertion region, multiple dummy cells. The method further includes selecting a first dummy cell from the dummy cells, determining, by the computer processor and based on a location of the first dummy cell, an illegal overlap with the first dummy cell, and removing, by the computer processor and from the dummy cells, the first dummy cell. The method further includes inserting, by the computer processor, on the circuit design, and after removing the first dummy cell, the dummy cells to obtain a modified circuit design, and presenting the modified circuit design.

Abstract: Implementations of the present disclosure involve a system and/or method for minimum cost cycle removal from a directed graph. The system determines if a provided graph contains any cycles by assigning each vertex an integer value and comparing the integer values of vertices connected by an edge. When the value of a starting vertex is greater than an ending vertex, a cycle is present. The system then determines which edges may be removed in order to minimize the cost of breaking the cycle. The system generates a linear cost function that is equal to the sum of a cost to remove an edge multiplied by a corresponding binary variable. Constraints are generated to ensure that the result does not have any cycles. The system then solves for the minimum of the linear cost function by utilizing the constraints. The value of the binary variables may then be used to determine which edges to remove.

Abstract: Implementations of the present disclosure involve a system and/or method for minimum cost cycle removal from a directed graph. The system determines if a provided graph contains any cycles by assigning each vertex an integer value and comparing the integer values of vertices connected by an edge. When the value of a starting vertex is greater than an ending vertex, a cycle is present. The system then determines which edges may be removed in order to minimize the cost of breaking the cycle. The system generates a linear cost function that is equal to the sum of a cost to remove an edge multiplied by a corresponding binary variable. Constraints are generated to ensure that the result does not have any cycles. The system then solves for the minimum of the linear cost function by utilizing the constraints. The value of the binary variables may then be used to determine which edges to remove.

Abstract: Aspects of the invention relate to hybrid hotspot detection techniques. The hybrid hotspot detection techniques combine machine learning classification, pattern matching and process simulation. A machine learning model, along with false hotspots and false non-hotspots for pattern matching, is determined based on training patterns. The determined machine learning model is then used to classify patterns in a layout design into three categories: preliminary hotspots, preliminary non-hotspots and potential hotspots. Pattern matching is then employed to identify false positives and false negatives in the first two categories. Process simulation is employed to identify boundary hotspots in the last category.

Abstract: Aspects of the invention relate to hybrid hotspot detection techniques. The hybrid hotspot detection techniques combine machine learning classification, pattern matching and process simulation. A machine learning model, along with false hotspots and false non-hotspots for pattern matching, is determined based on training patterns. The determined machine learning model is then used to classify patterns in a layout design into three categories: preliminary hotspots, preliminary non-hotspots and potential hotspots. Pattern matching is then employed to identify false positives and false negatives in the first two categories. Process simulation is employed to identify boundary hotspots in the last category.

Abstract: Architecture that utilizes web search implicitly to assist users in improving writing and associated productivity. The architecture extends the authoring experience of applications of office suite applications which can draw on a web search engine to offer contextual suggestions for revision, word auto-complete, and text prediction. Web-based research and reference to users is enabled as the user writes or revises text. Suggestions are made as to how to complete a phrase or sentence using data from networks such as the Internet or intranet, to how a user how revises a word or phrase in an already-written sentence using data from the network, and to problems in writing style/writing rules. Paragraph analysis is performed to find improper language usage or errors. Prediction and revision suggestions are extracted from web search or enterprise search document summaries, and intent of the user to obtain word completion, revision assistance, and prediction suggestions is identified.