Patents by Inventor Duo Ding

Duo Ding has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240411366
    Abstract: Disclosed is a wearable motion capture glove based on a flexible optical fiber, relating to the field of motion capture. The wearable motion capture glove includes a glove body, multiple motion acquisition sensing devices, and a glove packaging tool. Each motion acquisition sensing device includes a data acquisition and processing module, a circuit splint, and a flexible polymer profiled optical fiber. The data acquisition and processing module includes a motion capture data acquisition module, and a motion capture data processing module. The flexible optical fiber and the motion capture data acquisition module are firmly packaged using the circuit splint and the glove packaging tool, and then are fixed to a corresponding position of a finger joint of a wearer, such that the glove can be worn more closely to the finger joint, and data acquisition is more stable and accurate.
    Type: Application
    Filed: January 8, 2024
    Publication date: December 12, 2024
    Inventors: Bin LIU, Qi WANG, Xiyou LIANG, Tiancheng DONG, Zijing DING, Yuandong XIE, Mengdi MIAO, Libo TAN, Yuxin CHEN, Duo XU, Qinyang SONG
  • Publication number: 20240389558
    Abstract: A method for mass rearing of Telenomus remus includes the following steps: (1) establishing a Telenomus remus population of a Corcyra cephalonica strain; (2) collecting Corcyra cephalonica eggs laid by Corcyra cephalonica on the day, and fixing the Corcyra cephalonica eggs on a sticker; (3) inoculating female Telenomus remus of the Corcyra cephalonica strain in the step (1) into the Corcyra cephalonica eggs in the step (2); and (4) after 24 h to 48 h of a parasitism, taking parasitic Corcyra cephalonica eggs out, and feeding the parasitic Corcyra cephalonica eggs under the following conditions: a temperature: 26±1° C., a relative humidity: 65±5%, and a photoperiod: L: D=14:10, where long axes of the Corcyra cephalonica eggs in the step (2) have a length of 0.48 mm to 0.60 mm. The method of the present disclosure has great significance for the long-term control of pests of the Noctuidae family.
    Type: Application
    Filed: May 14, 2024
    Publication date: November 28, 2024
    Applicants: YUNNAN TOBACCO CO., LTD. KUNMING BRANCH, YUNNAN PUSHER BIOTECHNOLOGY CO., LTD.
    Inventors: Yonghui XIE, Zhengling LIU, Dekai NING, Hongming LI, Zhonglong LIN, Jingyu SHI, Zhijiang WANG, Aimin SHI, Yu SHEN, Youguo ZHAN, Xiaofei GU, Dingguo SHI, Facong QIAN, Shiyou DENG, Duo WANG, Dongya XU, Linqing TIAN, Yuanshen WANG, Qinglin RAO, Xianlong DING, Zhuoheng LI
  • Patent number: 12150474
    Abstract: A cooling cigarette filter and a cigarette are disclosed. The cooling cigarette filter comprises a cooling section (2). The cooling section (2) comprises a cooling stick (201) formed from paper (5). The cooling stick (201) has one or more holes (202) communicating two ends of the cooling stick. And the surface of the paper (5) is coated with a cooling material. The cooling cigarette filter has the advantages of ensuring the amount of smoke and lowering the temperature of the smoke entering the mouth. Through the combination design of the structure of the cooling stick and the type and amount of the cooling material, the smoke can flow out of a smoke generation section rapidly and smoothly And the temperature of the high-temperature smoke before entering the mouth can be significantly lowered, thereby improving the comfort and satisfaction of smoking.
    Type: Grant
    Filed: October 24, 2018
    Date of Patent: November 26, 2024
    Assignee: CHINA TOBACCO HUNAN INDUSTRIAL CO., LTD.
    Inventors: Wei Luo, Kejun Zhong, Wen Du, Lanying Xie, Liangsheng Qin, Jianhui Wen, Duo Ding, Guoyong Xie, Jianxin Ren, Zhiwei Sun
  • Patent number: 12137730
    Abstract: A cooling cigarette filter and a smoking product are provided. The cooling cigarette filter comprises a cooling section. The cooling section is provided with one or more channels connecting two ends of the cooling section, and an inner surface of each channel is coated with a cooling material. The cooling material comprises an inorganic phase change material and PEG, and the inorganic phase change material comprises at least one of Na2CO3·10H2O, CH3COONa·3H2O, CaCl2·4H2O, and Na2SO4·10H2O. The cooling cigarette filter has the advantages of ensuring the amount of smoke and lowering the temperature of the smoke entering the mouth, especially in the cooling section. Through the combination design of the structure of the cooling stick and the type and amount of the cooling material, the smoke can flow out of a smoke generation section rapidly and smoothly.
    Type: Grant
    Filed: February 20, 2019
    Date of Patent: November 12, 2024
    Assignee: CHINA TOBACCO HUNAN INDUSTRIAL CO., LTD.
    Inventors: Wei Luo, Kejun Zhong, Jianfu Liu, Lanying Xie, Liangsheng Qin, Wen Du, Jianhua Yi, Xinqiang Yin, Duo Ding, Jianhui Wen, Guoyong Xie
  • Publication number: 20220079215
    Abstract: A cooling cigarette filter and a smoking product are provided. The cooling cigarette filter comprises a cooling section. The cooling section is provided with one or more channels connecting two ends of the cooling section, and an inner surface of each channel is coated with a cooling material. The cooling material comprises an inorganic phase change material and PEG, and the inorganic phase change material comprises at least one of Na2CO3.10H2O, CH3COONa.3H2O, CaCl2.4H2O, and Na2SO4.10H2O. The cooling cigarette filter has the advantages of ensuring the amount of smoke and lowering the temperature of the smoke entering the mouth, especially in the cooling section. Through the combination design of the structure of the cooling stick and the type and amount of the cooling material, the smoke can flow out of a smoke generation section rapidly and smoothly.
    Type: Application
    Filed: February 20, 2019
    Publication date: March 17, 2022
    Applicant: CHINA TOBACCO HUNAN INDUSTRIAL CO., LTD.
    Inventors: Wei Luo, Kejun Zhong, Jianfu Liu, Lanying Xie, Liangsheng Qin, Wen Du, Jianhua Yi, Xinqiang Yin, Duo Ding, Jianhui Wen, Guoyong Xie
  • Publication number: 20210315268
    Abstract: A cooling cigarette filter and a cigarette are disclosed. The cooling cigarette filter comprises a cooling section (2). The cooling section (2) comprises a cooling stick (201) formed from paper (5). The cooling stick (201) has one or more holes (202) communicating two ends of the cooling stick. And the surface of the paper (5) is coated with a cooling material. The cooling cigarette filter has the advantages of ensuring the amount of smoke and lowering the temperature of the smoke entering the mouth. Through the combination design of the structure of the cooling stick and the type and amount of the cooling material, the smoke can flow out of a smoke generation section rapidly and smoothly And the temperature of the high-temperature smoke before entering the mouth can be significantly lowered, thereby improving the comfort and satisfaction of smoking.
    Type: Application
    Filed: October 24, 2018
    Publication date: October 14, 2021
    Applicant: CHINA TOBACCO HUNAN INDUSTRIAL CO., LTD.
    Inventors: Wei Luo, Kejun Zhong, Wen Du, Lanying Xie, Liangsheng Qin, Jianhui Wen, Duo Ding, Guoyong Xie, Jianxin Ren, Zhiwei Sun
  • Patent number: 10635849
    Abstract: A method for enhancing a chip layout may include obtaining the chip layout including a first layer including first and second tracks, a first route occupying the first track, and an open net including open terminals. The method may further include grouping the open terminals into at least a first subset of open terminals, calculating, based on the first subset, a region of interest (ROI), determining that neither the first track nor the second track within the ROI can be used to connect all the open terminals in the first subset, determining that the first track can be used to connect all the open terminals in the first subset after moving the first route from the first track to the second track, moving, the first route from the first track to the second track, and attempting to connect all the open terminals in the first subset using the first track.
    Type: Grant
    Filed: May 22, 2019
    Date of Patent: April 28, 2020
    Assignee: Oracle International Corporation
    Inventors: Tanushriya Singh, Akshay Sharma, Duo Ding, Chen Dan Dong
  • Publication number: 20190272355
    Abstract: A method for enhancing a chip layout may include obtaining the chip layout including a first layer including first and second tracks, a first route occupying the first track, and an open net including open terminals. The method may further include grouping the open terminals into at least a first subset of open terminals, calculating, based on the first subset, a region of interest (ROI), determining that neither the first track nor the second track within the ROI can be used to connect all the open terminals in the first subset, determining that the first track can be used to connect all the open terminals in the first subset after moving the first route from the first track to the second track, moving, the first route from the first track to the second track, and attempting to connect all the open terminals in the first subset using the first track.
    Type: Application
    Filed: May 22, 2019
    Publication date: September 5, 2019
    Applicant: Oracle International Corporation
    Inventors: Tanushriya Singh, Akshay Sharma, Duo Ding, Chen Dan Dong
  • Patent number: 10339252
    Abstract: A method for enhancing a chip layout may include obtaining the chip layout including a first layer including first and second tracks, a first route occupying the first track, and an open net including open terminals. The method may further include grouping the open terminals into at least a first subset of open terminals, calculating, based on the first subset, a region of interest (ROI), determining that neither the first track nor the second track within the ROI can be used to connect all the open terminals in the first subset, determining that the first track can be used to connect all the open terminals in the first subset after moving the first route from the first track to the second track, moving, the first route from the first track to the second track, and attempting to connect all the open terminals in the first subset using the first track.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: July 2, 2019
    Assignee: ORACLE INTERNATIONAL CORPORATION
    Inventors: Tanushriya Singh, Akshay Sharma, Duo Ding, Chen Dan Dong
  • Publication number: 20190065651
    Abstract: A method for enhancing a chip layout may include obtaining the chip layout including a first layer including first and second tracks, a first route occupying the first track, and an open net including open terminals. The method may further include grouping the open terminals into at least a first subset of open terminals, calculating, based on the first subset, a region of interest (ROI), determining that neither the first track nor the second track within the ROI can be used to connect all the open terminals in the first subset, determining that the first track can be used to connect all the open terminals in the first subset after moving the first route from the first track to the second track, moving, the first route from the first track to the second track, and attempting to connect all the open terminals in the first subset using the first track.
    Type: Application
    Filed: August 31, 2017
    Publication date: February 28, 2019
    Inventors: Tanushriya Singh, Akshay Sharma, Duo Ding, Chen Dan Dong
  • Patent number: 9390216
    Abstract: Systems, methods, and other embodiments associated with providing obstacle-avoidance bus routing for an integrated circuit design are described. In one embodiment, a bus routing tool is disclosed that generates a plurality of escape nodes to construct a three-dimensional routing solution graph. The bus routing tool probes a design space of the integrated circuit design to dynamically determine a location of each escape node while avoiding path blockages within the design space. By traversing the three-dimensional routing solution graph from a leaf escape node near a target location within the design space back to a root escape node near a source location within the design space, a candidate routing solution for routing a signal bus from the source location to the target location can be determined.
    Type: Grant
    Filed: October 20, 2014
    Date of Patent: July 12, 2016
    Assignee: ORACLE INTERNATIONAL CORPORATION
    Inventors: Duo Ding, Akshay Sharma, Huy Vo
  • Patent number: 9330224
    Abstract: A method for manipulating a circuit design includes receiving multiple dummy cell modification parameters, selecting, by a computer processor and based on the dummy cell modification parameters, a dummy cell insertion region on a circuit design, and generating, in the dummy cell insertion region, multiple dummy cells. The method further includes selecting a first dummy cell from the dummy cells, determining, by the computer processor and based on a location of the first dummy cell, an illegal overlap with the first dummy cell, and removing, by the computer processor and from the dummy cells, the first dummy cell. The method further includes inserting, by the computer processor, on the circuit design, and after removing the first dummy cell, the dummy cells to obtain a modified circuit design, and presenting the modified circuit design.
    Type: Grant
    Filed: April 30, 2014
    Date of Patent: May 3, 2016
    Assignee: Oracle International Corporation
    Inventors: Duo Ding, Srinivas Sanivarapu, Lai-ching Lydia So, Joseph Curt Peters, Carl Alfred Shisler, Gary Lynn Fowler, Thuvan Le, Kaiwha Peng, Tao Hou, Wilson Fai Chin
  • Publication number: 20160110490
    Abstract: Systems, methods, and other embodiments associated with providing obstacle-avoidance bus routing for an integrated circuit design are described. In one embodiment, a bus routing tool is disclosed that generates a plurality of escape nodes to construct a three-dimensional routing solution graph. The bus routing tool probes a design space of the integrated circuit design to dynamically determine a location of each escape node while avoiding path blockages within the design space. By traversing the three-dimensional routing solution graph from a leaf escape node near a target location within the design space back to a root escape node near a source location within the design space, a candidate routing solution for routing a signal bus from the source location to the target location may be determined.
    Type: Application
    Filed: October 20, 2014
    Publication date: April 21, 2016
    Inventors: Duo DING, Akshay SHARMA, Huy VO
  • Publication number: 20150317425
    Abstract: A method for manipulating a circuit design includes receiving multiple dummy cell modification parameters, selecting, by a computer processor and based on the dummy cell modification parameters, a dummy cell insertion region on a circuit design, and generating, in the dummy cell insertion region, multiple dummy cells. The method further includes selecting a first dummy cell from the dummy cells, determining, by the computer processor and based on a location of the first dummy cell, an illegal overlap with the first dummy cell, and removing, by the computer processor and from the dummy cells, the first dummy cell. The method further includes inserting, by the computer processor, on the circuit design, and after removing the first dummy cell, the dummy cells to obtain a modified circuit design, and presenting the modified circuit design.
    Type: Application
    Filed: April 30, 2014
    Publication date: November 5, 2015
    Applicant: Oracle International Corporation
    Inventors: Duo Ding, Srinivas Sanivarapu, Lai-ching Lydia So, Joseph Curt Peters, Carl Alfred Shisler, Gary Lynn Fowler, Thuvan Le, Kaiwha Peng, Tao Hou, Wilson Fai Chin
  • Patent number: 9176732
    Abstract: Implementations of the present disclosure involve a system and/or method for minimum cost cycle removal from a directed graph. The system determines if a provided graph contains any cycles by assigning each vertex an integer value and comparing the integer values of vertices connected by an edge. When the value of a starting vertex is greater than an ending vertex, a cycle is present. The system then determines which edges may be removed in order to minimize the cost of breaking the cycle. The system generates a linear cost function that is equal to the sum of a cost to remove an edge multiplied by a corresponding binary variable. Constraints are generated to ensure that the result does not have any cycles. The system then solves for the minimum of the linear cost function by utilizing the constraints. The value of the binary variables may then be used to determine which edges to remove.
    Type: Grant
    Filed: August 28, 2013
    Date of Patent: November 3, 2015
    Assignee: Oracle International Corporation
    Inventors: Ashutosh Chakraborty, Wonjoon Choi, Duo Ding, Rajendran Panda
  • Publication number: 20150067644
    Abstract: Implementations of the present disclosure involve a system and/or method for minimum cost cycle removal from a directed graph. The system determines if a provided graph contains any cycles by assigning each vertex an integer value and comparing the integer values of vertices connected by an edge. When the value of a starting vertex is greater than an ending vertex, a cycle is present. The system then determines which edges may be removed in order to minimize the cost of breaking the cycle. The system generates a linear cost function that is equal to the sum of a cost to remove an edge multiplied by a corresponding binary variable. Constraints are generated to ensure that the result does not have any cycles. The system then solves for the minimum of the linear cost function by utilizing the constraints. The value of the binary variables may then be used to determine which edges to remove.
    Type: Application
    Filed: August 28, 2013
    Publication date: March 5, 2015
    Applicant: Oracle International Corporation
    Inventors: Ashutosh Chakraborty, Wonjoon Choi, Duo Ding, Rajendran Panda
  • Patent number: 8504949
    Abstract: Aspects of the invention relate to hybrid hotspot detection techniques. The hybrid hotspot detection techniques combine machine learning classification, pattern matching and process simulation. A machine learning model, along with false hotspots and false non-hotspots for pattern matching, is determined based on training patterns. The determined machine learning model is then used to classify patterns in a layout design into three categories: preliminary hotspots, preliminary non-hotspots and potential hotspots. Pattern matching is then employed to identify false positives and false negatives in the first two categories. Process simulation is employed to identify boundary hotspots in the last category.
    Type: Grant
    Filed: July 26, 2011
    Date of Patent: August 6, 2013
    Assignee: Mentor Graphics Corporation
    Inventors: Juan Andres Torres Robles, Salma Mostafa Fahmy, Peter Louiz Rezk Beshay, Kareem Madkour, Fedor G Pikus, Jen-Yi Wuu, Duo Ding
  • Publication number: 20130031518
    Abstract: Aspects of the invention relate to hybrid hotspot detection techniques. The hybrid hotspot detection techniques combine machine learning classification, pattern matching and process simulation. A machine learning model, along with false hotspots and false non-hotspots for pattern matching, is determined based on training patterns. The determined machine learning model is then used to classify patterns in a layout design into three categories: preliminary hotspots, preliminary non-hotspots and potential hotspots. Pattern matching is then employed to identify false positives and false negatives in the first two categories. Process simulation is employed to identify boundary hotspots in the last category.
    Type: Application
    Filed: July 26, 2011
    Publication date: January 31, 2013
    Inventors: Juan Andres Torres Robles, Salma Mostafa Fahmy, Peter Louiz Rezk Beshay, Kareem Madkour, Fedor G. Pikus, Jen-Yi Wuu, Duo Ding
  • Publication number: 20120297294
    Abstract: Architecture that utilizes web search implicitly to assist users in improving writing and associated productivity. The architecture extends the authoring experience of applications of office suite applications which can draw on a web search engine to offer contextual suggestions for revision, word auto-complete, and text prediction. Web-based research and reference to users is enabled as the user writes or revises text. Suggestions are made as to how to complete a phrase or sentence using data from networks such as the Internet or intranet, to how a user how revises a word or phrase in an already-written sentence using data from the network, and to problems in writing style/writing rules. Paragraph analysis is performed to find improper language usage or errors. Prediction and revision suggestions are extracted from web search or enterprise search document summaries, and intent of the user to obtain word completion, revision assistance, and prediction suggestions is identified.
    Type: Application
    Filed: May 17, 2011
    Publication date: November 22, 2012
    Applicant: MICROSOFT CORPORATION
    Inventors: Matthew Robert Scott, Ming Zhou, Duo Ding, Xingping Jiang, Jonathan Y. Tien, Gang Chen, Hsiao-Wuen Hon, Andrea Jessee