Abstract: A semiconductor memory device having built-in error-correction capabilities, which comprises a primary array containing a plurality of memory cells; a redundancy array containing at least one replacement cell for replacing at least one defective cell in the primary array, wherein the defective cell is identified by a control signal and the control signal varies according to a defective state of the defective cell over time; and a switching circuit comprising a reprogrammable logic array that is coupled to the primary array and the redundancy array for receiving the control signal to switch a cell signal of the defective cell to the replacement cell.

Abstract: A semiconductor memory device having built-in error-correction capabilities, which comprises a primary array containing a plurality of memory cells; a redundancy array containing at least one replacement cell for replacing at least one defective cell in the primary array, wherein the defective cell is identified by a control signal and the control signal varies according to a defective state of the defective cell over time; and a switching circuit comprising a reprogrammable logic array that is coupled to the primary array and the redundancy array for receiving the control signal to switch a cell signal of the defective cell to the replacement cell.

Abstract: A re-programmable logic array includes at least one input and at least one output. An input capacitive device is coupled to the at least one input. Internal gating devices are coupled to the input capacitive device, and an output capacitive device is coupled to the internal gating devices and the at least one output. Signal generating circuitry for controlling the internal gating devices is further provided. The internal gating devices are designed to be controlled to establish a connection between one of the at least one input and one of the at least one output.