Patents by Inventor Duofeng Yue
Duofeng Yue has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9842895Abstract: An integrated circuit contains a thin film resistor in which a body of the thin film resistor is disposed over a lower dielectric layer in a system of interconnects in the integrated circuit. Heads of the thin film resistor are disposed over electrodes which are interconnect elements in the lower dielectric layer, which provide electrical connections to a bottom surface of the thin film resistor. Top surfaces of the electrodes are substantially coplanar with a top surface of the lower dielectric layer. A top surface of the thin film resistor is free of electrical connections. An upper dielectric layer is disposed over the thin film resistor.Type: GrantFiled: February 29, 2016Date of Patent: December 12, 2017Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Pinghai Hao, Fuchao Wang, Duofeng Yue
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Publication number: 20160197135Abstract: An integrated circuit contains a thin film resistor in which a body of the thin film resistor is disposed over a lower dielectric layer in a system of interconnects in the integrated circuit. Heads of the thin film resistor are disposed over electrodes which are interconnect elements in the lower dielectric layer, which provide electrical connections to a bottom surface of the thin film resistor. Top surfaces of the electrodes are substantially coplanar with a top surface of the lower dielectric layer. A top surface of the thin film resistor is free of electrical connections. An upper dielectric layer is disposed over the thin film resistor.Type: ApplicationFiled: February 29, 2016Publication date: July 7, 2016Inventors: Pinghai HAO, Fuchao WANG, Duofeng YUE
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Patent number: 9305688Abstract: An integrated circuit contains a thin film resistor in which a body of the thin film resistor is disposed over a lower dielectric layer in a system of interconnects in the integrated circuit. Heads of the thin film resistor are disposed over electrodes which are interconnect elements in the lower dielectric layer, which provide electrical connections to a bottom surface of the thin film resistor. Top surfaces of the electrodes are substantially coplanar with a top surface of the lower dielectric layer. A top surface of the thin film resistor is free of electrical connections. An upper dielectric layer is disposed over the thin film resistor.Type: GrantFiled: October 4, 2013Date of Patent: April 5, 2016Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: PingHai Hao, Fuchao Wang, Duofeng Yue
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Publication number: 20140184381Abstract: An integrated circuit contains a thin film resistor in which a body of the thin film resistor is disposed over a lower dielectric layer in a system of interconnects in the integrated circuit. Heads of the thin film resistor are disposed over electrodes which are interconnect elements in the lower dielectric layer, which provide electrical connections to a bottom surface of the thin film resistor. Top surfaces of the electrodes are substantially coplanar with a top surface of the lower dielectric layer. A top surface of the thin film resistor is free of electrical connections. An upper dielectric layer is disposed over the thin film resistor.Type: ApplicationFiled: October 4, 2013Publication date: July 3, 2014Applicant: Texas Instruments IncorporatedInventors: PingHai HAO, Fuchao WANG, Duofeng Yue
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Publication number: 20100041241Abstract: A process for void free deposition of dielectric films over high aspect ratio structures using HDP CVD. In a dielectric liner deposition step and the etch to deposition ratio is increased and the deposition pressure is reduced to reduce the aspect ratio of the gap and to deposit a dielectric sidewall on the gap with a significant slope.Type: ApplicationFiled: August 12, 2009Publication date: February 18, 2010Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Joseph A. GALLEGOS, Bill Alan WOFFORD, Edward L. MICKLER, Duofeng YUE
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Publication number: 20100032801Abstract: An capacitor is formed in an interlevel dielectric (ILD) layer of the integrated circuit (IC) by etching vertical trenches through the ILD and depositing conformal layers of a bottom electrode metal, a capacitor dielectric and a top electrode metal. The capacitor can attain a capacitance density of 20 nanofarads/mm2 in a 1 micron thick ILD, and is suitable for replacing external capacitors in a circuit containing the IC with external circuit elements. The disclosed fabrication methods are compatible with aluminum or copper interconnects.Type: ApplicationFiled: August 10, 2009Publication date: February 11, 2010Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Jarvis Benjamin Jacobs, Max Walthour Lippitt, Scott Kelly Montgomery, Robert William Murto, Byron Lovell Williams, Duofeng Yue
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Patent number: 7511350Abstract: The invention provides a semiconductor device, a method of manufacture therefore and a method for manufacturing an integrated circuit including the same. The semiconductor device, among other elements, may include a gate structure located over a substrate, the gate structure including a gate dielectric layer and gate electrode layer. The semiconductor device may further include source/drain regions located in/over the substrate and adjacent the gate structure, and a nickel alloy silicide located in the source/drain regions, the nickel alloy silicide having an amount of indium located therein.Type: GrantFiled: January 23, 2008Date of Patent: March 31, 2009Assignee: Texas Instruments IncorporatedInventors: Peijun J. Chen, Duofeng Yue, Amitabh Jain, Sue Crank, Thomas D. Bonifield, Homi Mogul
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Patent number: 7422968Abstract: The present invention provides a method for manufacturing a semiconductor device, and a method for manufacturing an integrated circuit including the semiconductor devices. The method for manufacturing a semiconductor device (100) , among other steps, includes forming a gate structure (120) over a substrate (110) and forming source/drain regions (190) in the substrate (110) proximate the gate structure (120). The method further includes subjecting the gate structure (120) and substrate (110) to a dry etch process and placing fluorine in the source/drain regions to form fluorinated source/drains (320) subsequent to subjecting the gate structure (120) and substrate (110) to the dry etch process. Thereafter, the method includes forming metal silicide regions (510, 520) in the gate structure (120) and the fluorinated source/drains (320).Type: GrantFiled: July 29, 2004Date of Patent: September 9, 2008Assignee: Texas Instruments IncorporatedInventors: Jiong-Ping Lu, Clint Montgomery, Lindsey Hall, Donald Miles, Duofeng Yue, Thomas D. Bonifiield
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Patent number: 7397046Abstract: Methods (300, 400) are described for calibrating the implantation angle of an ion implanter utilized in the manufacture of semiconductor products. One method (300) includes implanting (330) phosphorous ions into a pilot wafer held by a wafer platen held at a starting implantation angle in the ion implanter. The phosphorous implantation into a p-doped substrate of the pilot or blank wafer, for example, forms a semiconductive sheet. The method (300) then includes changing the implantation angle (340), and implanting another wafer (330) with phosphorous ions. The angle changing (340) and implanting (330) of other wafers continues in this manner until all wafers or angles are implanted (350) as desired. The phosphorous implanted wafers are then measured (360) with a four-point probe, for example, to obtain the sheet resistance of all the implanted wafers.Type: GrantFiled: December 29, 2004Date of Patent: July 8, 2008Assignee: Texas Instruments IncorporatedInventors: Duofeng Yue, Jeffrey Loewecke, JieJie Xu, Thomas Patrick Conroy
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Publication number: 20080128837Abstract: The invention provides a semiconductor device, a method of manufacture therefore and a method for manufacturing an integrated circuit including the same. The semiconductor device, among other elements, may include a gate structure located over a substrate, the gate structure including a gate dielectric layer and gate electrode layer. The semiconductor device may further include source/drain regions located in/over the substrate and adjacent the gate structure, and a nickel alloy silicide located in the source/drain regions, the nickel alloy silicide having an amount of indium located therein.Type: ApplicationFiled: January 23, 2008Publication date: June 5, 2008Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Peijun J. Chen, Duofeng Yue, Amitabh Jain, Sue Crank, Thomas D. Bonifield, Homi Mogul
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Patent number: 7355255Abstract: The present invention provides a semiconductor device, a method of manufacture therefore and a method for manufacturing an integrated circuit including the same. The semiconductor device, among other elements, may include a substrate (110), as well as a nickel silicide region (170) located over the substrate (110), the nickel silicide region (170) having an amount of indium located therein.Type: GrantFiled: February 26, 2007Date of Patent: April 8, 2008Assignee: Texas Instruments IncorporatedInventors: Peijun J. Chen, Duofeng Yue, Amitabh Jain, Sue E. Crank, Thomas D. Bonifield, Homi C. Mogul
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Patent number: 7344985Abstract: The invention provides a semiconductor device, a method of manufacture therefore and a method for manufacturing an integrated circuit including the same. The semiconductor device, among other elements, may include a gate structure located over a substrate, the gate structure including a gate dielectric layer and gate electrode layer. The semiconductor device may further include source/drain regions located in/over the substrate and adjacent the gate structure, and a nickel alloy silicide located in the source/drain regions, the nickel alloy silicide having an amount of indium located therein.Type: GrantFiled: October 20, 2006Date of Patent: March 18, 2008Assignee: Texas Instruments IncorporatedInventors: Peijun J. Chen, Duofeng Yue, Amitabh Jain, Sue Crank, Thomas D. Bonifield, Homi Mogul
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Patent number: 7256121Abstract: The present invention provides a method for forming an interconnect on a semiconductor substrate 100. The method includes forming an opening 230 over an inner surface of the opening 130, the depositing forming a reentrant profile near a top portion of the opening 130. A portion of barrier 230 is etched, which removes at least a portion of the barrier 230 to reduce the reentrant profile. The etching also removes at least a portion of the barrier 230 layer at the bottom of the opening 130.Type: GrantFiled: December 2, 2004Date of Patent: August 14, 2007Assignee: Texas Instruments IncorporatedInventors: Duofeng Yue, Stephan Grunow, Satyavolu S. Papa Rao, Noel M. Russell, Montray Leavy
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Publication number: 20070141840Abstract: The present invention provides a semiconductor device, a method of manufacture therefore and a method for manufacturing an integrated circuit including the same. The semiconductor device, among other elements, may include a substrate (110), as well as a nickel silicide region (170) located over the substrate (110), the nickel silicide region (170) having an amount of indium located therein.Type: ApplicationFiled: February 26, 2007Publication date: June 21, 2007Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Peijun Chen, Duofeng Yue, Amitabh Jain, Sue Crank, Thomas Bonifield, Homi Mogul
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Patent number: 7211516Abstract: The present invention provides a semiconductor device, a method of manufacture therefore and a method for manufacturing an integrated circuit including the same. The semiconductor device, among other elements, may include a substrate (110), as well as a nickel silicide region (170) located over the substrate (110), the nickel silicide region (170) having an amount of indium located therein.Type: GrantFiled: April 1, 2005Date of Patent: May 1, 2007Assignee: Texas Instruments IncorporatedInventors: Peijun J. Chen, Duofeng Yue, Amitabh Jain, Sue Crank, Thomas D. Bonifield, Homi Mogul
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Patent number: 7208398Abstract: The present invention provides a method of manufacturing a metal silicide electrode (100) for a semiconductor device (110). The method comprises depositing by physical vapor deposition, halogen atoms (120) and transition metal atoms (130) to form a halogen-containing metal layer (140) on a semiconductor substrate (150). The halogen-containing metal layer and the semiconductor substrate are reacted to form a metal silicide electrode. Other aspects of the present invention include a method of manufacturing an integrated circuit (400) comprising the metal silicide electrode.Type: GrantFiled: July 30, 2004Date of Patent: April 24, 2007Assignee: Texas Instruments IncorporatedInventors: Peijun J. Chen, Duofeng Yue, Douglas E. Mercer, Noel Russell
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Patent number: 7208409Abstract: Fluorine containing regions (70) are formed in the source and drain regions (60) of the MOS transistor. A metal layer (90) is formed over the fluorine containing regions (70) and the source and drain regions (60). The metal layer is reacted with the underlying fluorine containing regions to form a metal silicide.Type: GrantFiled: March 7, 2005Date of Patent: April 24, 2007Assignee: Texas Instruments IncorporatedInventors: Jiong-Ping Lu, Duofeng Yue, Xiaozhan Liu, Donald S. Miles, Lance S. Robertson
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Patent number: 7199032Abstract: The present invention provides a method of manufacturing a metal silicide electrode (100) for a semiconductor device (110). The method comprises implanting small atoms into an nMOS semiconductor substrate (130) to a depth (132) no greater than about 30 nanometers into the nMOS semiconductor substrate. The method further comprises depositing a transition metal layer (400) over the nMOS semiconductor substrate. The transition metal layer and the nMOS semiconductor substrate are reacted to form the metal silicide electrode. Other aspects of the present invention include a method of manufacturing an integrated circuit (700).Type: GrantFiled: July 30, 2004Date of Patent: April 3, 2007Assignee: Texas Instruments IncorporatedInventors: Duofeng Yue, Peijun J. Chen, Sue Ellen Crank, Thomas D. Bonifield, Jiong-Ping Lu, Jie-Jie Xu
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Publication number: 20070049022Abstract: The invention provides a semiconductor device, a method of manufacture therefore and a method for manufacturing an integrated circuit including the same. The semiconductor device, among other elements, may include a gate structure located over a substrate, the gate structure including a gate dielectric layer and gate electrode layer. The semiconductor device may further include source/drain regions located in/over the substrate and adjacent the gate structure, and a nickel alloy silicide located in the source/drain regions, the nickel alloy silicide having an amount of indium located therein.Type: ApplicationFiled: October 20, 2006Publication date: March 1, 2007Applicant: Texas Instruments, IncorporatedInventors: Peijun Chen, Duofeng Yue, Amitabh Jain, Sue Crank, Thomas Bonifield, Homi Mogul
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Publication number: 20060223295Abstract: The present invention provides a semiconductor device, a method of manufacture therefore and a method for manufacturing an integrated circuit including the same. The semiconductor device, among other elements, may include a substrate (110), as well as a nickel silicide region (170) located over the substrate (110), the nickel silicide region (170) having an amount of indium located therein.Type: ApplicationFiled: April 1, 2005Publication date: October 5, 2006Applicant: Texas Instruments, IncorporatedInventors: Peijun Chen, Duofeng Yue, Amitabh Jain, Sue Crank, Thomas Bonifield, Homi Mogul