Abstract: Disclosed is a digital phase-locked-loop including: a time-to-digital converter (TDC) configured to output a digital bit based on an input clock and a reference clock, in which the TDC includes: a first arbiter group configured to compensate for a phase difference between the input clock and the reference clock with a first average offset and output a first logic value; a second arbiter group configured to compensate for a phase difference between the input clock and the reference clock with a second average offset and output a second logic value; and a signal processor configured to output the digital bit based on the first and second logic values.

Abstract: Disclosed is a digital phase-locked-loop including: a time-to-digital converter (TDC) configured to output a digital bit based on an input clock and a reference clock, in which the TDC includes: a first arbiter group configured to compensate for a phase difference between the input clock and the reference clock with a first average offset and output a first logic value; a second arbiter group configured to compensate for a phase difference between the input clock and the reference clock with a second average offset and output a second logic value; and a signal processor configured to output the digital bit based on the first and second logic values.

Abstract: There is provided a baseband structure of a transceiver. In an embodiment, a baseband structure of a transceiver includes a Variable Gain Amplifier (VGA) configured to amplify an input signal by controlling a gain, one or more Fixed Gain Amplifiers (FGAs) connected in series to the VGA and configured to amplify an output signal of the VGA, and one or more selection switches configured to selectively operate the FGAs. In accordance with the present invention, since a plurality of FGAs is selectively driven according to a necessary gain and an LPFG includes an FGA, power consumption and the size of a chip can be reduced and the overall performance of a transceiver can be improved.