Abstract: A memory device can include a nonvolatile memory (NVM) cell array, data path circuits, coupled between the NVM cell array and an output of the device, that are configured to enable access to the NVM cell array via a plurality of bit lines. A first charge pump can generate a first voltage supply. A second charge pump can generate a second voltage supply. Switch circuits are configured to, in a first mode, couple the first voltage supply to data path circuits, and in a second mode, couple the second voltage supply to the data path circuits. The first charge pump, the second charge pump, the switch circuits, the data path circuits and the NVM cell array are formed with the same integrated circuit substrate. Corresponding methods and systems are also disclosed.

Abstract: A memory device can include a plurality of banks, each bank including a memory cell array of nonvolatile (NV) memory cells; a plurality of charge pumps, including a first charge pump and second charge pump; and a switch circuit. The switch circuit can be configured to, in a first mode, connect the first charge pump to first circuits of the banks and isolate the second charge pump from the first circuits, and in a second mode, isolate the first charge pump from the first circuits and connect the second charge pump to the first circuits.