Patents by Inventor Dureseti Chidambarrao

Dureseti Chidambarrao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10628544
    Abstract: A technique for optimizing integrated circuit (IC) designs based on interaction between multiple integration design rules is provided. For a plurality of IC features, total risk values are determined based on multiple integration design rules. IC features are ordered based on the total risk values. IC features having the highest total risk values are selected based on a threshold count. An IC design is clipped around the high-risk IC features. An overall failure rate is simulated for the clipped area. If the overall failure rate exceeds a threshold, a predicted failure rate for each design rule that applies to IC features within the clipped area is calculated. A high-risk design rule is identified based on the predicted failure rates. The IC design is modified such that a difference between a design rule value of the high-risk design rule and a corresponding design value is reduced.
    Type: Grant
    Filed: September 25, 2017
    Date of Patent: April 21, 2020
    Assignee: International Business Machines Corporation
    Inventors: Dureseti Chidambarrao, Jason D. Hibbeler, Dongbing Shao, Steven Zebertavage
  • Patent number: 10614190
    Abstract: Embodiments include method, systems and computer program products for designing physical devices using an iterative floorplan methodology. The method creating, using a processor, a rough floorplan, wherein the rough floorplan includes one or more tiles and estimates for one or more components associated with the floorplan. The processor converts the estimates for the one or more components to stresses and displacements/distortions associated with the one or more tiles. The processor further generates distortion data from the displacements/distortions associated with the one or more tiles. The processor further compares the distortion data to a threshold. The processor further creates a finalized floorplan based on the rough floorplan in response to the distortion data being below the threshold.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: April 7, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Dureseti Chidambarrao, Frank Malgioglio
  • Patent number: 10592627
    Abstract: A technique for optimizing integrated circuit (IC) designs based on interaction between multiple integration design rules is provided. For a plurality of IC features, total risk values are determined based on multiple integration design rules. IC features are ordered based on the total risk values. IC features having the highest total risk values are selected based on a threshold count. An IC design is clipped around the high-risk IC features. An overall failure rate is simulated for the clipped area. If the overall failure rate exceeds a threshold, a predicted failure rate for each design rule that applies to IC features within the clipped area is calculated. A high-risk design rule is identified based on the predicted failure rates. The IC design is modified such that a difference between a design rule value of the high-risk design rule and a corresponding design value is reduced.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: March 17, 2020
    Assignee: International Business Machines Corporation
    Inventors: Dureseti Chidambarrao, Jason D. Hibbeler, Dongbing Shao, Steven Zebertavage
  • Publication number: 20200004910
    Abstract: Embodiments include method, systems and computer program products for designing physical devices using an iterative floorplan methodology. The method creating, using a processor, a rough floorplan, wherein the rough floorplan includes one or more tiles and estimates for one or more components associated with the floorplan. The processor converts the estimates for the one or more components to stresses and displacements/distortions associated with the one or more tiles. The processor further generates distortion data from the displacements/distortions associated with the one or more tiles. The processor further compares the distortion data to a threshold. The processor further creates a finalized floorplan based on the rough floorplan in response to the distortion data being below the threshold.
    Type: Application
    Filed: June 29, 2018
    Publication date: January 2, 2020
    Inventors: Dureseti Chidambarrao, Frank Malgioglio
  • Publication number: 20190095550
    Abstract: A technique for optimizing integrated circuit (IC) designs based on interaction between multiple integration design rules is provided. For a plurality of IC features, total risk values are determined based on multiple integration design rules. IC features are ordered based on the total risk values. IC features having the highest total risk values are selected based on a threshold count. An IC design is clipped around the high-risk IC features. An overall failure rate is simulated for the clipped area. If the overall failure rate exceeds a threshold, a predicted failure rate for each design rule that applies to IC features within the clipped area is calculated. A high-risk design rule is identified based on the predicted failure rates. The IC design is modified such that a difference between a design rule value of the high-risk design rule and a corresponding design value is reduced.
    Type: Application
    Filed: September 25, 2017
    Publication date: March 28, 2019
    Inventors: Dureseti Chidambarrao, Jason D. Hibbeler, Dongbing Shao, Steven Zebertavage
  • Publication number: 20190095551
    Abstract: A technique for optimizing integrated circuit (IC) designs based on interaction between multiple integration design rules is provided. For a plurality of IC features, total risk values are determined based on multiple integration design rules. IC features are ordered based on the total risk values. IC features having the highest total risk values are selected based on a threshold count. An IC design is clipped around the high-risk IC features. An overall failure rate is simulated for the clipped area. If the overall failure rate exceeds a threshold, a predicted failure rate for each design rule that applies to IC features within the clipped area is calculated. A high-risk design rule is identified based on the predicted failure rates. The IC design is modified such that a difference between a design rule value of the high-risk design rule and a corresponding design value is reduced.
    Type: Application
    Filed: November 17, 2017
    Publication date: March 28, 2019
    Inventors: Dureseti Chidambarrao, Jason D. Hibbeler, Dongbing Shao, Steven Zebertavage
  • Patent number: 9754071
    Abstract: Various embodiments include approaches for analyzing integrated circuit (IC) designs. In some cases, an approach includes: defining extraction parameters for the design of the IC for each of a set of failure modes; testing the design of the IC for a failure mode in the set of failure modes; identifying a defined extraction parameter from the design of the IC for at least one of the set of failure modes; correlating the identified defined extracted parameter and each of the at least one failure mode for the design of the IC; and creating a normalized parameter equation representing the correlation of the identified defined extraction parameter with the at least one failure mode for the design of the IC in numerical form.
    Type: Grant
    Filed: February 19, 2016
    Date of Patent: September 5, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Haraprasad Nanjundappa, Basanth Jagannathan, Laura S. Chadwick, Dureseti Chidambarrao, Christopher V. Baiocco
  • Publication number: 20170242952
    Abstract: Various embodiments include approaches for analyzing integrated circuit (IC) designs. In some cases, an approach includes: defining extraction parameters for the design of the IC for each of a set of failure modes; testing the design of the IC for a failure mode in the set of failure modes; identifying a defined extraction parameter from the design of the IC for at least one of the set of failure modes; correlating the identified defined extracted parameter and each of the at least one failure mode for the design of the IC; and creating a normalized parameter equation representing the correlation of the identified defined extraction parameter with the at least one failure mode for the design of the IC in numerical form.
    Type: Application
    Filed: February 19, 2016
    Publication date: August 24, 2017
    Inventors: Haraprasad Nanjundappa, Basanth Jagannathan, Laura S. Chadwick, Dureseti Chidambarrao, Christopher V. Baiocco
  • Patent number: 9646124
    Abstract: In a system and method, a design layout defines a transistor, a local layout effect (LLE)-inducing feature and shapes, including a non-uniform shape, that illustrate separation between the channel region and LLE-inducing feature. Layout information for the non-uniform shape, including minimum and maximum distances between the channel region and LLE-inducing feature, is extracted. Based on this layout information, a first width of a first portion of the non-uniform shape, which is associated with the maximum distance, and a second width of a second portion of the non-uniform shape, which is associated with the minimum distance, are derived and used to calculate the non-uniform shape's contribution to the value of a model parameter adjuster. The value of the model parameter adjuster is then calculated based on a sum of contributions from all shapes and used to generate a compact model for modeling a performance attribute of the transistor within the IC.
    Type: Grant
    Filed: June 24, 2015
    Date of Patent: May 9, 2017
    Assignee: International Business Machines Corporation
    Inventors: Dureseti Chidambarrao, Richard Q. Williams
  • Patent number: 9536039
    Abstract: Various embodiments include computer-implemented methods, computer program products and systems for modeling at least one feature in an integrated circuit (IC) layout for an inter-layer effect. In some cases, approaches include a computer-implemented method of modeling at least one feature in an IC layout for an inter-level effect, the method including: building a set of shape measurement regions each connected with an edge of the at least one feature; determining a set of shape parameters for each shape measurement region in the set of shape measurement regions; and creating a column vector representing each shape measurement region using the set of shape parameters, the column vector representing the inter-layer effect of the at least one feature, wherein the inter-layer effect includes a physical relationship between the at least one feature and another feature on a distinct level of the IC layout.
    Type: Grant
    Filed: April 6, 2016
    Date of Patent: January 3, 2017
    Assignee: International Business Machines Corporation
    Inventors: Shayak Banerjee, Dureseti Chidambarrao, Dongbing Shao
  • Publication number: 20160378888
    Abstract: In a system and method, a design layout defines a transistor, a local layout effect (LLE)-inducing feature and shapes, including a non-uniform shape, that illustrate separation between the channel region and LLE-inducing feature. Layout information for the non-uniform shape, including minimum and maximum distances between the channel region and LLE-inducing feature, is extracted. Based on this layout information, a first width of a first portion of the non-uniform shape, which is associated with the maximum distance, and a second width of a second portion of the non-uniform shape, which is associated with the minimum distance, are derived and used to calculate the non-uniform shape's contribution to the value of a model parameter adjuster. The value of the model parameter adjuster is then calculated based on a sum of contributions from all shapes and used to generate a compact model for modeling a performance attribute of the transistor within the IC.
    Type: Application
    Filed: June 24, 2015
    Publication date: December 29, 2016
    Inventors: Dureseti Chidambarrao, Richard Q. Williams
  • Publication number: 20160217249
    Abstract: Various embodiments include computer-implemented methods, computer program products and systems for modeling at least one feature in an integrated circuit (IC) layout for an inter-layer effect. In some cases, approaches include a computer-implemented method of modeling at least one feature in an IC layout for an inter-level effect, the method including: building a set of shape measurement regions each connected with an edge of the at least one feature; determining a set of shape parameters for each shape measurement region in the set of shape measurement regions; and creating a column vector representing each shape measurement region using the set of shape parameters, the column vector representing the inter-layer effect of the at least one feature, wherein the inter-layer effect includes a physical relationship between the at least one feature and another feature on a distinct level of the IC layout.
    Type: Application
    Filed: April 6, 2016
    Publication date: July 28, 2016
    Inventors: Shayak Banerjee, Dureseti Chidambarrao, Dongbing Shao
  • Patent number: 9401424
    Abstract: Methods of forming a semiconductor device are provided. A method of forming a semiconductor device may include forming a stressing layer on a substrate. The method may include doping the stressing layer with dopants. The method may include forming a silicide layer on the stressing layer. Moreover, the stressing layer may include a first lattice constant different from a second lattice constant of the substrate.
    Type: Grant
    Filed: July 8, 2014
    Date of Patent: July 26, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Huajie Chen, Dureseti Chidambarrao, Omer H. Dokumaci
  • Patent number: 9342648
    Abstract: Various embodiments include computer-implemented methods, computer program products and systems for modeling at least one feature in an integrated circuit (IC) layout for an inter-layer effect. In some cases, approaches include a computer-implemented method of modeling at least one feature in an IC layout for an inter-level effect, the method including: building a set of shape measurement regions each connected with an edge of the at least one feature; determining a set of shape parameters for each shape measurement region in the set of shape measurement regions; and creating a column vector representing each shape measurement region using the set of shape parameters, the column vector representing the inter-layer effect of the at least one feature, wherein the inter-layer effect includes a physical relationship between the at least one feature and another feature on a distinct level of the IC layout.
    Type: Grant
    Filed: June 10, 2014
    Date of Patent: May 17, 2016
    Assignee: International Business Machines Corporation
    Inventors: Shayak Banerjee, Dureseti Chidambarrao, Dongbing Shao
  • Patent number: 9311443
    Abstract: Apparatus, method and computer program product for reducing overlay errors during a semiconductor photolithographic mask design process flow. The method obtains data representing density characteristics of a photo mask layout design; predicts stress induced displacements based on said obtained density characteristics data; and corrects the mask layout design data by specifying shift movement of individual photo mask design shapes to pre-compensate for predicted displacements. To obtain data representing density characteristics, the method merges pieces of data that are combined to make a photo mask to obtain a full reticle field data set. The merge includes a merge of data representing density characteristic driven stress effects. The density characteristics data for the merged reticle data are then computed.
    Type: Grant
    Filed: June 17, 2014
    Date of Patent: April 12, 2016
    Inventors: Dureseti Chidambarrao, James A. Culp, Paul C. Parries, Ian P. Stobert
  • Patent number: 9305999
    Abstract: A stack pad layers including a first pad oxide layer, a pad nitride layer, and a second pad oxide layer are formed on a semiconductor-on-insulator (SOI) substrate. A deep trench extending below a top surface or a bottom surface of a buried insulator layer of the SOI substrate and enclosing at least one top semiconductor region is formed by lithographic methods and etching. A stress-generating insulator material is deposited in the deep trench and recessed below a top surface of the SOI substrate to form a stress-generating buried insulator plug in the deep trench. A silicon oxide material is deposited in the deep trench, planarized, and recessed. The stack of pad layer is removed to expose substantially coplanar top surfaces of the top semiconductor layer and of silicon oxide plugs. The stress-generating buried insulator plug encloses, and generates a stress to, the at least one top semiconductor region.
    Type: Grant
    Filed: February 27, 2013
    Date of Patent: April 5, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Huilong Zhu, Brian J. Greene, Dureseti Chidambarrao, Gregory G. Freeman
  • Publication number: 20150363536
    Abstract: Apparatus, method and computer program product for reducing overlay errors during a semiconductor photolithographic mask design process flow. The method obtains data representing density characteristics of a photo mask layout design; predicts stress induced displacements based on said obtained density characteristics data; and corrects the mask layout design data by specifying shift movement of individual photo mask design shapes to pre-compensate for predicted displacements. To obtain data representing density characteristics, the method merges pieces of data that are combined to make a photo mask to obtain a full reticle field data set. The merge includes a merge of data representing density characteristic driven stress effects. The density characteristics data for the merged reticle data are then computed.
    Type: Application
    Filed: June 17, 2014
    Publication date: December 17, 2015
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Dureseti Chidambarrao, James A. Culp, Paul C. Parries, Ian P. Stobert
  • Publication number: 20150356230
    Abstract: Various embodiments include computer-implemented methods, computer program products and systems for modeling at least one feature in an integrated circuit (IC) layout for an inter-layer effect. In some cases, approaches include a computer-implemented method of modeling at least one feature in an IC layout for an inter-level effect, the method including: building a set of shape measurement regions each connected with an edge of the at least one feature; determining a set of shape parameters for each shape measurement region in the set of shape measurement regions; and creating a column vector representing each shape measurement region using the set of shape parameters, the column vector representing the inter-layer effect of the at least one feature, wherein the inter-layer effect includes a physical relationship between the at least one feature and another feature on a distinct level of the IC layout.
    Type: Application
    Filed: June 10, 2014
    Publication date: December 10, 2015
    Inventors: Shayak Banerjee, Dureseti Chidambarrao, Dongbing Shao
  • Patent number: 9082877
    Abstract: A complementary metal oxide semiconductor (CMOS) device including a substrate including a first active region and a second active region, wherein each of the first active region and second active region of the substrate are separated by from one another by an isolation region. A n-type semiconductor device is present on the first active region of the substrate, in which the n-type semiconductor device includes a first portion of a gate structure. A p-type semiconductor device is present on the second active region of the substrate, in which the p-type semiconductor device includes a second portion of the gate structure. A connecting gate portion provides electrical connectivity between the first portion of the gate structure and the second portion of the gate structure. Electrical contact to the connecting gate portion is over the isolation region, and is not over the first active region and/or the second active region.
    Type: Grant
    Filed: May 30, 2014
    Date of Patent: July 14, 2015
    Assignee: International Business Machines Corporation
    Inventors: Yue Liang, Dureseti Chidambarrao, Brian J. Greene, William K. Henson, Unoh Kwon, Shreesh Narasimha, Xiaojun Yu
  • Publication number: 20150179536
    Abstract: A physical test integrated circuit has a plurality of repeating circuit portions corresponding to an integrated circuit design. A first of the portions is fabricated with a nominal block mask location, and additional ones of the portions are deliberately fabricated with predetermined progressive increased offset of the block mask location from the nominal block mask location. For each of the portions, the difference in threshold voltage between a first field effect transistor and a second field effect transistor is determined. The predetermined progressive increased offset of the block mask location is in a direction from the first field effect transistor to the second field effect transistor. The block mask overlay tolerance is determined at a value of the progressive increased offset corresponding to an inflection of the difference in threshold voltage from a zero difference. A method for on-chip monitoring, and corresponding circuits, are also disclosed.
    Type: Application
    Filed: February 28, 2015
    Publication date: June 25, 2015
    Inventors: Emrah Acar, Aditya Bansal, Dureseti Chidambarrao, Liang-Teck Pang, Amith Singhee