Abstract: In one embodiment, a semiconductor nanowire having a monotonically increasing width with distance from a middle portion toward adjoining semiconductor pads is provided. A semiconductor link portion having tapered end portions is lithographically patterned. During the thinning process that forms a semiconductor nanowire, the taper at the end portions of the semiconductor nanowire provides enhanced mechanical strength to prevent structural buckling or bending. In another embodiment, a semiconductor nanowire having bulge portions are formed by preventing the thinning of a semiconductor link portion at pre-selected positions. The bulge portions having a greater width than a middle portion of the semiconductor nanowire provides enhanced mechanical strength during thinning of the semiconductor link portion so that structural damage to the semiconductor nanowire is avoided during thinning.

Abstract: The present invention provides a semiconducting device including a gate region positioned on a mesa portion of a substrate; and a nitride liner positioned on the gate region and recessed surfaces of the substrate adjacent to the gate region, the nitride liner providing a stress to a device channel underlying the gate region. The stress produced on the device channel is a longitudinal stress on the order of about 275 MPa to about 450 MPa.

Abstract: An eFuse, includes: a substrate and an insulating layer disposed on the substrate; a first layer including a single crystal or polycrystalline silicon disposed on the insulating layer; a second layer including a single crystal or polycrystalline silicon germanium disposed on the first layer, and a third layer including a silicide disposed on the second layer. The Ge has a final concentration in a range of approximately five percent to approximately twenty-five percent.

Abstract: A semiconductor structure is provided that includes an asymmetric gate stack located on a surface of high k gate dielectric. The asymmetric gate stack includes a first portion and a second portion, wherein the first portion has a different threshold voltage than the second portion. The first portion of the inventive asymmetric gate stack includes, from bottom to top, a threshold voltage adjusting material and at least a first conductive spacer, while the second portion of the inventive asymmetric gate stack includes at least a second conductive spacer over the gate dielectric. In some embodiments, the second conductive spacer is in direct contact with the underlying high k gate dielectric, while in other embodiments, in which the first and second conductive spacers are comprised of different conductive materials, the base of the second conductive spacer is in direct contact with the threshold adjusting material.

Abstract: A semiconductor nanowire having two semiconductor pads on both ends is suspended over a substrate. Stress-generating liner portions are formed over the two semiconductor pads, while a middle portion of the semiconductor nanowire is exposed. A gate dielectric and a gate electrode are formed over the middle portion of the semiconductor nanowire while the semiconductor nanowire is under longitudinal stress due to the stress-generating liner portions. The middle portion of the semiconductor nanowire is under a built-in inherent longitudinal stress after removal of the stress-generating liners because the formation of the gate dielectric and the gate electrode locks in the strained state of the semiconductor nanowire. Source and drain regions are formed in the semiconductor pads to provide a semiconductor nanowire transistor. A middle-of-line (MOL) dielectric layer may be formed directly on the source and drain pads.

Abstract: Prototype semiconductor structures each including a semiconductor link portion and two adjoined pad portions are formed by lithographic patterning of a semiconductor layer on a dielectric material layer. The sidewalls of the semiconductor link portions are oriented to maximize hole mobility for a first-type semiconductor structures, and to maximize electron mobility for a second-type semiconductor structures. Thinning by oxidation of the semiconductor structures reduces the width of the semiconductor link portions at different rates for different crystallographic orientations. The widths of the semiconductor link portions are predetermined so that the different amount of thinning on the sidewalls of the semiconductor link portions result in target sublithographic dimensions for the resulting semiconductor nanowires after thinning.

Abstract: A method and computer program product for modeling a semiconductor transistor device structure having an active device area, a gate structure, and including a conductive line feature connected to the gate structure and disposed above the active device area, the conductive line feature including a conductive landing pad feature disposed near an edge of the active device area in a circuit to be modeled. The method includes determining a distance between an edge defined by the landing pad feature to an edge of the active device area, and, from modeling a lithographic rounding effect of the landing pad feature, determining changes in width of the active device area as a function of the distance between an edge defined by the landing pad feature to an edge of the active device area. From these data, an effective change in active device area width (deltaW adder) is related to the determined distance.

Abstract: A semiconductor structure is provided that includes at least one asymmetric gate stack located on a surface of a semiconductor structure. The at least one asymmetric gate stack includes, from bottom to top, a high k gate dielectric, a sloped threshold voltage adjusting material layer and a gate conductor. A method of forming such a semiconductor structure is also provided in which a line of sight deposition process is used in forming the sloped threshold voltage adjusting material layer in which the deposition is tilted within respect to a horizontal surface of a semiconductor structure.

Abstract: The present invention relates to a semiconductor-on-insulator (SOI) substrate having one or more device regions. Each device region comprises at least a base semiconductor substrate layer and a semiconductor device layer with a buried insulator layer located therebetween, while the semiconductor device layer is supported by one or more vertical insulating pillars. The vertical insulating pillars each preferably has a ledge extending between the base semiconductor substrate layer and the semiconductor device layer. The SOI substrates of the present invention can be readily formed from a precursor substrate structure with a “floating” semiconductor device layer that is spaced apart from the base semiconductor substrate layer by an air gap and is supported by one or more vertical insulating pillars. The air gap is preferably formed by selective removal of a sacrificial layer located between the base semiconductor substrate layer and the semiconductor device layer.

Abstract: A method for forming a semiconductor substrate structure is provided. A compressively strained SiGe layer is formed on a silicon substrate. Atoms are ion-implanted onto the SiGe layer to cause end-of-range damage. Annealing is performed to relax the strained SiGe layer. During the annealing, interstitial dislocation loops are formed as uniformly distributed in the SiGe layer. The interstitial dislocation loops provide a basis for nucleation of misfit dislocations between the SiGe layer and the silicon substrate. Since the interstitial dislocation loops are distributed uniformly, the misfit locations are also distributed uniformly, thereby relaxing the SiGe layer. A tensilely strained silicon layer is formed on the relaxed SiGe layer.

Abstract: The present invention provides a method in which a low-resistance connection between the MOS channel and silicided source/drain regions is provided that has an independence from the extension ion implant process as well as device overlap capacitance. The method of the present invention broadly includes selectively removing outer spacers of an MOS structure and then selectively plating a metallic or intermetallic material on exposed portions of a semiconductor substrate that were previously protected by the outer spacers. The present invention also provides a semiconductor structure that is formed utilizing the method. The semiconductor structure includes a low-resistance connection between the silicided source/drain regions and the channel regions which includes a selectively plated metallic or intermetallic material.

Abstract: A fuse includes a fuse link region, a first region and a second region. The fuse link region electrically connects the first region to the second region. A SiGe layer is disposed only in the fuse link region and the first region.

Abstract: A finFET and its method for fabrication include a gate electrode formed over a channel region of a semiconductor fin. The semiconductor fin has a crystallographic orientation and an axially specific piezoresistance coefficient. The gate electrode is formed with an intrinsic stress determined to influence, and preferably optimize, charge carrier mobility within the channel region. To that end, the intrinsic stress preferably provides induced axial stresses within the gate electrode and semiconductor fin channel region that complement the axially specific piezoresistance coefficient.

Abstract: Prototype semiconductor structures each including a semiconductor link portion and two adjoined pad portions are formed by lithographic patterning of a semiconductor layer on a dielectric material layer. The sidewalls of the semiconductor link portions are oriented to maximize hole mobility for a first-type semiconductor structures, and to maximize electron mobility for a second-type semiconductor structures. Thinning by oxidation of the semiconductor structures reduces the width of the semiconductor link portions at different rates for different crystallographic orientations. The widths of the semiconductor link portions are predetermined so that the different amount of thinning on the sidewalls of the semiconductor link portions result in target sublithographic dimensions for the resulting semiconductor nanowires after thinning.

Abstract: A contiguous block of a stack of two heterogeneous semiconductor layers is formed over an insulator region such as shallow trench isolation. A portion of the contiguous block is exposed to an etch, while another portion is masked during the etch. The etch removes an upper semiconductor layer selective to a lower semiconductor layer in the exposed portion. The etch mask is removed and the entirety of the lower semiconductor layer within the exposed region is metallized. A first metal semiconductor alloy vertically abutting the insulator region is formed, while exposed surfaces of the stack of two heterogeneous semiconductor layers, which comprises the materials of the upper semiconductor layer, are concurrently metallized to form a second metal semiconductor alloy. An inflection point for current and, consequently, a region of flux divergence are formed at the boundary of the two metal semiconductor alloys.

Abstract: A design rule that determines a degree of overlap between two design elements in two adjoining levels by estimating a physical overlap area, or an “intersect area,” of corresponding structures in a semiconductor chip is provided. The estimation of the physical intersect area may factor in line edge biasing, critical dimension tolerance, overlay tolerance, and corner rounding to provide an accurate estimate of a physical area for each of the structures corresponding to the two design elements. The intersect area is employed as a metric to determine compliance with a ground rule, i.e., the ground rule is specified in terms of the intersect region. Other derived quantities such as electrical resistance, electromigration resistance, expected yield may be calculated from the intersect area, and may be advantageously employed to optimize the design data.

Abstract: A semiconductor nanowire having two semiconductor pads on both ends is suspended over a substrate. Stress-generating liner portions are formed over the two semiconductor pads, while a middle portion of the semiconductor nanowire is exposed. A gate dielectric and a gate electrode are formed over the middle portion of the semiconductor nanowire while the semiconductor nanowire is under longitudinal stress due to the stress-generating liner portions. The middle portion of the semiconductor nanowire is under a built-in inherent longitudinal stress after removal of the stress-generating liners because the formation of the gate dielectric and the gate electrode locks in the strained state of the semiconductor nanowire. Source and drain regions are formed in the semiconductor pads to provide a semiconductor nanowire transistor. A middle-of-line (MOL) dielectric layer may be formed directly on the source and drain pads.

Abstract: The present invention relates to a semiconductor-on-insulator (SOI) substrate having one or more device regions. Each device region comprises at least a base semiconductor substrate layer and a semiconductor device layer with a buried insulator layer located therebetween, while the semiconductor device layer is supported by one or more vertical insulating pillars. The vertical insulating pillars each preferably has a ledge extending between the base semiconductor substrate layer and the semiconductor device layer. The SOI substrates of the present invention can be readily formed from a precursor substrate structure with a “floating” semiconductor device layer that is spaced apart from the base semiconductor substrate layer by an air gap and is supported by one or more vertical insulating pillars. The air gap is preferably formed by selective removal of a sacrificial layer located between the base semiconductor substrate layer and the semiconductor device layer.

Abstract: The present invention provides a semiconductor device having dual silicon nitride liners and a reformed silicide layer and related methods for the manufacture of such a device. The reformed silicide layer has a thickness and resistance substantially similar to a silicide layer not exposed to the formation of the dual silicon nitride liners. A first aspect of the invention provides a method for use in the manufacture of a semiconductor device comprising the steps of applying a first silicon nitride liner to a silicide layer, removing a portion of the first silicon nitride liner, reforming a portion of the silicide layer removed during the removal step, and applying a second silicon nitride liner to the silicide layer.

Abstract: A semiconductor nanowire having two semiconductor pads on both ends is suspended over a substrate. Stress-generating liner portions are formed over the two semiconductor pads, while a middle portion of the semiconductor nanowire is exposed. A gate dielectric and a gate electrode are formed over the middle portion of the semiconductor nanowire while the semiconductor nanowire is under longitudinal stress due to the stress-generating liner portions. The middle portion of the semiconductor nanowire is under a built-in inherent longitudinal stress after removal of the stress-generating liners because the formation of the gate dielectric and the gate electrode locks in the strained state of the semiconductor nanowire. Source and drain regions are formed in the semiconductor pads to provide a semiconductor nanowire transistor. A middle-of-line (MOL) dielectric layer may be formed directly on the source and drain pads.