Abstract: The present invention relates to a method of manufacturing sidewall spacers on a memory device. The method comprises forming sidewall spacers on a memory device having a memory array region and at least one peripheral circuit region by forming a first sidewall spacer adjacent to a word line in the memory array region and a second sidewall spacer adjacent to a transistor in the peripheral circuit region. The first sidewall spacer has a first thickness and the second sidewall spacer has a second thickness, wherein the second thickness is greater than the first thickness.

Abstract: A transistor structure includes a semiconductor substrate; a conductor having a lower block in the semiconductor substrate and an upper block on the semiconductor substrate; a metal layer positioned on the upper block; a cap layer positioned on the metal layer; an upper insulation layer positioned at least on sidewalls of the metal layer and the cap layer; and a lower insulation layer positioned on sidewalls of the upper block of the conductor.