Patents by Inventor Durgam Vahia

Durgam Vahia has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Shared memory multiprocessor memory model verification system and method
    Patent number: 6892286
    Abstract: A system and method for verifying a memory consistency model for a shared memory multiprocessor computer systems generates random instructions to run on the processors, saves the results of the running of the instructions, and analyzes the results to detect a memory subsystem error if the results fall outside of the space of possible outcomes consistent with the memory consistency model. A precedence relationship of the results is determined by uniquely identifying results of a store location with each result distinct to allow association of a read result value to the instruction that created the read result value. A precedence graph with static, direct and derived edges identifies errors when a cycle is detected that indicates results that are inconsistent with memory consistency model rules.
    Type: Grant
    Filed: September 30, 2002
    Date of Patent: May 10, 2005
    Assignee: Sun Microsystems, Inc.
    Inventors: Sudheendra Hangal, Durgam Vahia, Juin-Yeu Lu, Chaiyasit Manovit
  • Shared memory multiprocessor memory model verification system and method
    Publication number: 20040064656
    Abstract: A system and method for verifying a memory consistency model for a shared memory multiprocessor computer systems generates random instructions to run on the processors, saves the results of the running of the instructions, and analyzes the results to detect a memory subsystem error if the results fall outside of the space of possible outcomes consistent with the memory consistency model. A precedence relationship of the results is determined by uniquely identifying results of a store location with each result distinct to allow association of a read result value to the instruction that created the read result value. A precedence graph with static, direct and derived edges identifies errors when a cycle is detected that indicates results that are inconsistent with memory consistency model rules.
    Type: Application
    Filed: September 30, 2002
    Publication date: April 1, 2004
    Inventors: Sudheendra Hangal, Durgam Vahia, Juin-Yeu Lu