Abstract: A system (102) and method for controlling the operation of an engine test apparatus (104) during a test cycle is provided. The system (102) includes an operator interface (106) for producing a control mode signal and a plurality of setpoints. The system (102) also includes a test controller (108) for receiving the control mode signal and the plurality of setpoints and responsively operating the engine test apparatus. The test controller (108) senses operating characteristics of the engine test apparatus (104). The test controller (108) also selectively operates engine test apparatus parameters in accordance with the control mode signal.

Abstract: A system and method for controlling the operation of an engine test apparatus during a test cycle is provided. The system includes an operator interface for producing a control mode signal and a plurality of setpoints. The system also includes a test controller for receiving the control mode signal and the plurality of setpoints and responsively operating the engine test apparatus. The test controller senses operating characteristics of the engine test apparatus. The test controller also selectively operates engine test apparatus parameters in accordance with the control mode signal.

Abstract: A system is disclosed that performs a plurality of measurements based on a set of preprogrammed instructions. The system includes a central processing unit (CPU) that has an internal primary and expansion bus. The internal primary bus includes a program memory and the internal expansion bus includes an I/O memory. The set of preprogrammed instructions resides in the program memory and defines a predetermined type of measurement. A standard bus couples the internal primary bus to one or more standard external devices, while a custom bus couples the internal expansion bus to one or more custom external devices. The custom bus includes an analog bus that provides for analog signal transmission to one or more custom external devices. At least one of the custom external devices receives a test signal, conditions the test signal and delivers data representing the conditioned test signal to the I/O memory.