Abstract: A device is provided that comprises a metallic substrate defining a plurality of openings, the openings having a first area. The openings form one or more heat dissipating elements having a second area. The device comprises a plurality of sites on a surface of the one or more heat dissipating elements. Each site is configured to receive a light emitting element. The device comprises a plurality of conductor elements having a third area. The conductor elements are physically separated from the one or more heat dissipating elements by the openings. The conductor elements are configured to enable electrical connections to the light emitting elements and are electrically isolated from the one or more heat dissipating elements.

Abstract: An LED light source is described herein, which comprises: a hollow heat sink having a top wall, a bottom opening, and a sidewall, the top wall including an upper surface and a lower surface, the upper surface having a central area and a peripheral area, and the top wall having at least one first hole in the peripheral area; an interposer being overmolded on the peripheral area and the lower surface, and extending through the at least one first hole; an LED package comprising at least one LED chip and mounted in the central area; an LED driver located within the hollow heat sink and positioned on a side of the interposer facing the bottom opening.

Abstract: A package is manufactured by placing a substrate, for example a lead frame, in a mold with a protection flange extending into a notch in the substrate around a contact surface. The protection flange impedes molding compound from reaching the contact surface reducing the need for a deflash step.

Abstract: A package is manufactured by placing a substrate, for example a lead frame, in a mold with a protection flange extending into a notch in the substrate around a contact surface. The protection flange impedes molding compound from reaching the contact surface reducing the need for a deflash step.

Abstract: An LED light source is described herein, which comprises: a hollow heat sink having a top wall, a bottom opening, and a sidewall, the top wall including an upper surface and a lower surface, the upper surface having a central area and a peripheral area, and the top wall having at least one first hole in the peripheral area; an interposer being overmolded on the peripheral area and the lower surface, and extending through the at least one first hole; an LED package comprising at least one LED chip and mounted in the central area; an LED driver located within the hollow heat sink and positioned on a side of the interposer facing the bottom opening.

Abstract: A package is manufactured by placing a substrate (10), for example a lead frame, in a mold (30) with a protection flange (38) extending into a notch (14) in the substrate (10) around a contact surface (12). The protection flange (38) impedes molding compound from reaching the contact surface reducing the need for a deflash step.

Abstract: A device is provided that comprises a metallic substrate defining a plurality of openings, the openings having a first area. The openings form one or more heat dissipating elements having a second area. The device comprises a plurality of sites on a surface of the one or more heat dissipating elements. Each site is configured to receive a light emitting element. The device comprises a plurality of conductor elements having a third area. The conductor elements are physically separated from the one or more heat dissipating elements by the openings. The conductor elements are configured to enable electrical connections to the light emitting elements and are electrically isolated from the one or more heat dissipating elements.

Abstract: A light emitting device is provided that includes an integral heat dissipation element. This heat dissipation element is included in the leadframe that is used to facilitate fabrication of the light emitting device, to provide a single common substrate that forms both the heat dissipation element and the conductive elements for coupling the light emitting device to external sources of power. The heat dissipation element may extend beyond the protective structure that surrounds the light emitting element to facilitate heat dissipation to the surrounding medium.

Abstract: A light emitting device is provided that includes an integral heat dissipation element. This heat dissipation element is included in the leadframe that is used to facilitate fabrication of the light emitting device, to provide a single common substrate that forms both the heat dissipation element and the conductive elements for coupling the light emitting device to external sources of power. The heat dissipation element may extend beyond the protective structure that surrounds the light emitting element to facilitate heat dissipation to the surrounding medium.

Abstract: A package is manufactured by placing a substrate (10), for example a lead frame, in a mold (30) with a protection flange (38) extending into a notch (14) in the substrate (10) around a contact surface (12). The protection flange (38) impedes molding compound from reaching the contact surface reducing the need for a deflash step.

Abstract: The invention relates to a multi-transistor, e.g. a two-transistor memory cell with an enhancement junction field effect transistor (JFET) as the access gate transistor. In one embodiment, the JFET is provided as a self-aligned JFET. Accordingly, and advantageous over the prior art, the invention allows for a method for manufacturing a multi-transistor, e.g. a two-transistor memory cell comprising a JFET as the access transistor without adding any additional masks and/or processing steps. Such a multi-transistor, e.g. a two-transistor memory cell according to invention, provides an improved reliability.

Abstract: A tunnel field effect transistor and a method of making the same. The transistor includes a semiconductor substrate. The transistor also includes a gate located on a major surface of the substrate. The transistor further includes a drain of a first conductivity type. The transistor also includes a source of a second conductivity type extending beneath the gate. The source is separated from the gate by a channel region and a gate dielectric. The transistor is operable to allow charge carrier tunnelling from an inversion layer through an upper surface of the source.

Abstract: Various exemplary embodiments relate to an isolation device including a semiconductor layer and an insulation layer. The insulation layer insulates a central portion of the semiconductor layer. A high voltage terminal connects to the insulation layer, a first low voltage terminal connects to a first non-insulated portion of the semiconductor layer, and a second low voltage terminal connects to a second non-insulated portion of the semiconductor layer. The first and second low voltage terminals are electrically connected via the semiconductor layer. A voltage applied to the high voltage terminal influences the conductance of the semiconductor layer. The high voltage terminal is galvanically isolated from the first and second low voltage terminals.

Abstract: A memory cell, the memory cell comprising a substrate, a nanowire extending along a vertical trench formed in the substrate, a control gate surrounding the nanowire, and a charge storage structure formed between the control gate and the nanowire.

Abstract: A memory cell (100) comprising a transistor, the transistor comprising a substrate (101), a first source/drain region (102), a second source/drain region (112), a gate (104) and a gate insulating layer (103) positioned between the substrate (101) and the gate (104), wherein the gate insulating layer (103) is in a direct contact with the substrate (101) and comprises charge traps (131) distributed over an entire volume of the gate insulating layer (101).

Abstract: Various exemplary embodiments relate to an isolation device including a semiconductor layer and an insulation layer. The insulation layer insulates a central portion of the semiconductor layer. A high voltage terminal connects to the insulation layer, a first low voltage terminal connects to a first non-insulated portion of the semiconductor layer, and a second low voltage terminal connects to a second non-insulated portion of the semiconductor layer. The first and second low voltage terminals are electrically connected via the semiconductor layer. A voltage applied to the high voltage terminal influences the conductance of the semiconductor layer. The high voltage terminal is galvanically isolated from the first and second low voltage terminals.

Abstract: A semiconductor chip has an integrated inductor, manufactured during back end of line processing. In particular, a loop (30) is formed in a metallization layer and a central region (32) of magnetic material is provided within the loop. The size of the central region is controlled so that it includes no more than five magnetic domains to achieve the desired properties.

Abstract: An optocoupler device facilitates on-chip galvanic isolation. In accordance with various example embodiments, an optocoupler circuit includes a silicon-on-insulator substrate having a silicon layer on a buried insulator layer, a silicon-based light-emitting diode (LED) having a silicon p-n junction in the silicon layer, and a silicon-based photodetector in the silicon layer. The LED and photodetector are respectively connected to galvanically isolated circuits in the silicon layer. A local oxidation of silicon (LOCOS) isolation material and the buried insulator layer galvanically isolate the first circuit from the second circuit to prevent charge carriers from moving between the first and second circuits. The LED and photodetector communicate optically to pass signals between the galvanically isolated circuits.

Abstract: An optocoupler device facilitates on-chip galvanic isolation. In accordance with various example embodiments, an optocoupler circuit includes a silicon-on-insulator substrate having a silicon layer on a buried insulator layer, a silicon-based light-emitting diode (LED) having a silicon p-n junction in the silicon layer, and a silicon-based photodetector in the silicon layer. The LED and photodetector are respectively connected to galvanically isolated circuits in the silicon layer. A local oxidation of silicon (LOCOS) isolation material and the buried insulator layer galvanically isolate the first circuit from the second circuit to prevent charge carriers from moving between the first and second circuits. The LED and photodetector communicate optically to pass signals between the galvanically isolated circuits.

Abstract: A tunnel field effect transistor and a method of making the same. The transistor includes a semiconductor substrate. The transistor also includes a gate located on a major surface of the substrate. The transistor further includes a drain of a first conductivity type. The transistor also includes a source of a second conductivity type extending beneath the gate. The source is separated from the gate by a channel region and a gate dielectric. The transistor is operable to allow charge carrier tunnelling from an inversion layer through an upper surface of the source.