Patents by Inventor Dusan Jevtic

Dusan Jevtic has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20050071043
    Abstract: A method for providing distributed material management and flow control in an integrated circuit (IC) factory. The IC factory comprises a factory stocker, a plurality of process bays and a factory transport agent for moving wafer cassettes between the bay and the stocker. Each of the bays comprises a bay stocker, a plurality of tools, a mini-stocker and a bay transport agent for moving wafers amongst the bay components. The apparatus uses partitioned stockers to facilitate deadlock avoidance or deadlock resolution. Additionally, various algorithms are used to detect wafer cassette movement situations where deadlocks may result from a wafer cassette movement within a bay and for resolving deadlocks when they occur.
    Type: Application
    Filed: November 15, 2004
    Publication date: March 31, 2005
    Inventors: Dusan Jevtic, Raja Sunkara
  • Patent number: 6845294
    Abstract: A method for providing distributed material management and flow control in an integrated circuit (IC) factory. The IC factory comprises a factory stocker, a plurality of process bays and a factory transport agent for moving wafer cassettes between the bay and the stocker. Each of the bays comprises a bay stocker, a plurality of tools, a mini-stocker and a bay transport agent for moving wafers amongst the bay components. The apparatus uses partitioned stockers to facilitate deadlock avoidance or deadlock resolution. Additionally, various algorithms are used to detect wafer cassette movement situations where deadlocks may result from a wafer cassette movement within a bay and for resolving deadlocks when they occur.
    Type: Grant
    Filed: January 6, 2004
    Date of Patent: January 18, 2005
    Assignee: Applied Materials, Inc.
    Inventors: Dusan Jevtic, Raja S. Sunkara
  • Publication number: 20040107021
    Abstract: A method for providing distributed material management and flow control in an integrated circuit (IC) factory. The IC factory comprises a factory stocker, a plurality of process bays and a factory transport agent for moving wafer cassettes between the bay and the stocker. Each of the bays comprises a bay stocker, a plurality of tools, a mini-stocker and a bay transport agent for moving wafers amongst the bay components. The apparatus uses partitioned stockers to facilitate deadlock avoidance or deadlock resolution. Additionally, various algorithms are used to detect wafer cassette movement situations where deadlocks may result from a wafer cassette movement within a bay and for resolving deadlocks when they occur.
    Type: Application
    Filed: January 6, 2004
    Publication date: June 3, 2004
    Inventors: Dusan Jevtic, Raja S. Sunkara
  • Patent number: 6684123
    Abstract: A factory interface for a multiple chamber semiconductor wafer processing cluster tool having a K-wafer load-lock (KWLL). The KWLL comprises a variable number of K+1 wafer slots assigned as inbound and outbound slots. Inbound slots are used to send up to K+1 wafers into the cluster tool and the same slots, denoted as outbound slots, are used for receiving up to K+1 wafers from the cluster tool. The K+1 slots are in the same volume that has to be pumped for wafers to enter the tool and vented for wafers that to leave the tool. These K+1 slots accommodate up to K wafers when accessed by a single blade robots from the tool or the factory interface, and up to K+1 wafers when the tool and factory interface are equipped with dual blade robots. Various KWLL loading methods can be selected to optimize the throughput of a wafer processing system using the KWLL. Such methods include wafer packing, reactive and gamma tolerant methods.
    Type: Grant
    Filed: June 26, 2001
    Date of Patent: January 27, 2004
    Assignee: Applied Materials, Inc.
    Inventors: Dusan Jevtic, Raja Sunkara
  • Patent number: 6580967
    Abstract: A method and apparatus for providing distributed material management and flow control in an integrated circuit (IC) factory. The IC factory comprises a factory stocker, a plurality of process bays and a factory transport agent for moving wafer cassettes between the bay and the stocker. Each of the bays comprises a bay stocker, a plurality of tools, a mini-stocker and a bay transport agent for moving wafers amongst the bay components. The apparatus uses partitioned stockers to facilitate deadlock avoidance or deadlock resolution. Additionally, various algorithms are used to detect wafer cassette movement situations where deadlocks may result from a wafer cassette movement within a bay and for resolving deadlocks when they occur.
    Type: Grant
    Filed: June 26, 2001
    Date of Patent: June 17, 2003
    Assignee: Applied Materials, Inc.
    Inventors: Dusan Jevtic, Raja S. Sunkara
  • Patent number: 6519498
    Abstract: A method and apparatus for analyzing schedules for multi-cluster tools that are used in semiconductor wafer processing and similar manufacturing applications. The method and apparatus comprise a schedule analyzer and a pass-through chamber manager. The apparatus allows the user to analyze N! possible scheduling routines (algorithms) for a given multi-cluster tool configuration and a given N-step process sequence. The invention derives a plurality of possible scheduling algorithms for a given set of input parameters and then compares the algorithms by allowing either the user or an automated process to assign each processing step within the proposed schedule a rank ordered priority. Other process or wafer movement parameters may also be given ranges such that the invention can automatically derive optimal schedules with respect to various parameter values.
    Type: Grant
    Filed: March 10, 2000
    Date of Patent: February 11, 2003
    Assignee: Applied Materials, Inc.
    Inventors: Dusan Jevtic, Mark Pool, Raja Sunkara
  • Publication number: 20030000468
    Abstract: A factory interface for a multiple chamber semiconductor wafer processing cluster tool having a K-wafer load-lock (KWLL). The KWLL comprises a variable number of K+1 wafer slots assigned as inbound and outbound slots. Inbound slots are used to send up to K+1 wafers into the cluster tool and the same slots, denoted as outbound slots, are used for receiving up to K+1 wafers from the cluster tool. The K+1 slots are in the same volume that has to be pumped for wafers to enter the tool and vented for wafers that to leave the tool. These K+1 slots accommodate up to K wafers when accessed by a single blade robots from the tool or the factory interface, and up to K+1 wafers when the tool and factory interface are equipped with dual blade robots. Various KWLL loading methods can be selected to optimize the throughput of a wafer processing system using the KWLL. Such methods include wafer packing, reactive and gamma tolerant methods.
    Type: Application
    Filed: June 26, 2001
    Publication date: January 2, 2003
    Applicant: Applied Materials, Inc.
    Inventors: Dusan Jevtic, Raja Sunkara
  • Publication number: 20020198623
    Abstract: A method and apparatus for providing distributed material management and flow control in an integrated circuit (IC) factory. The IC factory comprises a factory stocker, a plurality of process bays and a factory transport agent for moving wafer cassettes between the bay and the stocker. Each of the bays comprises a bay stocker, a plurality of tools, a mini-stocker and a bay transport agent for moving wafers amongst the bay components. The apparatus uses partitioned stockers to facilitate deadlock avoidance or deadlock resolution. Additionally, various algorithms are used to detect wafer cassette movement situations where deadlocks may result from a wafer cassette movement within a bay and for resolving deadlocks when they occur.
    Type: Application
    Filed: June 26, 2001
    Publication date: December 26, 2002
    Applicant: Applied Materials, Inc.
    Inventors: Dusan Jevtic, Raja S. Sunkara
  • Patent number: 6496746
    Abstract: A method and apparatus for producing schedules for a wafer in a multichamber semiconductor wafer processing tool comprising the steps of providing a trace defining a series of chambers that are visited by a wafer as the wafer is processed by the tool; initializing a sequence generator with a value of a variable defining initial wafer positioning within the tool; generating all successor variables for the initial variable value to produce a series of values of the variable that represent a partial schedule; backtracking through the series of variables to produce further partial schedules; and stopping the backtracking when all possible variable combinations are produced that represent all possible valid schedules for the trace. All the possible schedules are analyzed to determine a schedule that produces the highest throughput of all the schedules.
    Type: Grant
    Filed: March 13, 2001
    Date of Patent: December 17, 2002
    Assignee: Applied Materials, Inc.
    Inventor: Dusan Jevtic
  • Patent number: 6336204
    Abstract: A method and apparatus for handling deadlocks in a multichamber semiconductor wafer processing system known as a cluster tool. A plurality of software routines execute upon a sequencer of a cluster tool to perform deadlock avoidance, deadlock detection and deadlock resolution towards achieving optimal wafer throughput for a cluster tool.
    Type: Grant
    Filed: May 7, 1998
    Date of Patent: January 1, 2002
    Assignee: Applied Materials, Inc.
    Inventor: Dusan Jevtic
  • Publication number: 20010011198
    Abstract: A method and apparatus for producing schedules for a wafer in a multichamber semiconductor wafer processing tool comprising the steps of providing a trace defining a series of chambers that are visited by a wafer as the wafer is processed by the tool; initializing a sequence generator with a value of a variable defining initial wafer positioning within the tool; generating all successor variables for the initial variable value to produce a series of values of the variable that represent a partial schedule; backtracking through the series of variables to produce further partial schedules; and stopping the backtracking when all possible variable combinations are produced that represent all possible valid schedules for the trace. All the possible schedules are analyzed to determine a schedule that produces the highest throughput of all the schedules.
    Type: Application
    Filed: March 13, 2001
    Publication date: August 2, 2001
    Inventor: Dusan Jevtic
  • Patent number: 6224638
    Abstract: Apparatus and concomitant method for performing priority-based scheduling of wafer processing within a multiple chamber semiconductor wafer processing system (cluster tool) having a dual blade wafer transfer mechanism. The sequencer assigns priority values to the chambers in a cluster tool, then moves wafers from chamber to chamber in accordance with the assigned priorities. The sequencer is capable of determining the amount of time available before a priority move is to be performed and, if time is sufficient, the sequencer performs a non-priority move while waiting. The sequencer also dynamically varies assigned priorities depending upon the availability of chambers in the tool. Lastly, the sequencer prioritizes the chambers based upon the minimum time required for the wafer transfer mechanism to move the wafers in a particular stage.
    Type: Grant
    Filed: February 10, 2000
    Date of Patent: May 1, 2001
    Assignee: Applied Materials, Inc.
    Inventors: Dusan Jevtic, Srilakshmi Venkatesh
  • Patent number: 6201999
    Abstract: A method and apparatus for producing schedules for a wafer in a multichamber semiconductor wafer processing tool comprising the steps of providing a trace defining a series of chambers that are visited by a wafer as the wafer is processed by the tool; initializing a sequence generator with a value of a variable defining initial wafer positioning within the tool; generating all successor variables for the initial variable value to produce a series of values of the variable that represent a partial schedule; backtracking through the series of variables to produce further partial schedules; and stopping the backtracking when all possible variable combinations are produced that represent all possible valid schedules for the trace. All the possible schedules are analyzed to determine a schedule that produces the highest throughput of all the schedules.
    Type: Grant
    Filed: June 9, 1997
    Date of Patent: March 13, 2001
    Assignee: Applied Materials, Inc.
    Inventor: Dusan Jevtic
  • Patent number: 6074443
    Abstract: Apparatus and concomitant method for performing priority-based scheduling of wafer processing within a multiple chamber semiconductor wafer processing system (cluster tool) having a dual blade wafer transfer mechanism. The sequencer assigns priority values to the chambers in a cluster tool, then moves wafers from chamber to chamber in accordance with the assigned priorities. The sequencer is capable of determining the amount of time available before a priority move is to be performed and, if time is sufficient, the sequencer performs a non-priority move while waiting. The sequencer also dynamically varies assigned priorities depending upon the availability of chambers in the tool. Lastly, the sequencer prioritizes the chambers based upon the minimum time required for the wafer transfer mechanism to move the wafers in a particular stage.
    Type: Grant
    Filed: January 29, 1998
    Date of Patent: June 13, 2000
    Assignee: Applied Materials, Inc.
    Inventors: Srilakshmi Venkatesh, Dusan Jevtic
  • Patent number: 5928389
    Abstract: Apparatus and concomitant method for performing priority based scheduling of wafer processing within a multiple chamber semiconductor wafer processing system (cluster tool). The sequencer assigns priority values to the chambers in a cluster tool, then moves wafers from chamber to chamber in accordance with the assigned priorities. The sequencer is capable of determining the amount of time available before a priority move is to be performed and, if time is sufficient, the sequencer performs a non-priority move while waiting. The sequencer also dynamically varies assigned priorities depending upon the availability of chambers in the tool. Lastly, the sequencer prioritizes the chambers based upon the minimum time required for the robot to move the wafers in a particular stage.
    Type: Grant
    Filed: October 21, 1996
    Date of Patent: July 27, 1999
    Assignee: Applied Materials, Inc.
    Inventor: Dusan Jevtic