Patents by Inventor Dusan POSTULKA

Dusan POSTULKA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12588445
    Abstract: In an example, a method of manufacturing a semiconductor device includes providing a semiconductor substrate comprising an unpolished CZ silicon substrate, a substrate upper side, and a substrate lower side opposite to the substrate upper side. The method includes first annealing the semiconductor substrate at a first temperature in an inert environment for a first time. The method includes second annealing the semiconductor substrate at a second temperature in a wet oxidation environment for a second time. The first annealing dissolves inner wall oxide in bulk region voids and the second annealing fills the voids with semiconductor interstitials. In some examples, the CZ silicon substrate is provided from a CZ ingot grown in the presence of a magnetic field and using continuous counter-doping. The method provides, among other things, a CZ silicon substrate with reduced crystal originated particle (COP) defects, reduced oxygen concentration, and reduced radial resistivity variation.
    Type: Grant
    Filed: August 24, 2022
    Date of Patent: March 24, 2026
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: David Lysacek, Jan Hybl, Dusan Postulka, Juraj Jarina, Vit Janirek, Alexandra Senkova
  • Publication number: 20250259883
    Abstract: In an aspect, a process can include bonding a carrier substrate to a first major surface of a donor substrate; generating a laser damage zone within the donor substrate; bonding a processing substrate to a second major surface of the donor substrate, wherein the second major surface is opposite the first major surface; and separating (1) the processing substrate and a device portion of the donor substrate and (2) the carrier substrate and a remaining portion of the donor substrate from each other. In another aspect, an electronic device can include a device portion of a SiC substrate, wherein the device portion includes at least part of an electronic circuit element. A processing substrate can be bonded the device portion, wherein the processing substrate can withstand processing conditions when fabricating the electronic device.
    Type: Application
    Filed: February 13, 2024
    Publication date: August 14, 2025
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Karel KOCIAN, Dusan POSTULKA, Juraj JARINA
  • Publication number: 20250149377
    Abstract: A semiconductor substrate includes a handle wafer, an oxide layer formed on the handle wafer, and a device layer formed or disposed on the oxide layer. The device layer includes a first epitaxial silicon layer bonded to the oxide layer formed on the handle wafer, a layer of compensated silicon crystalline material formed or disposed on the first epitaxial silicon layer, and a second epitaxial silicon layer formed on the layer of compensated silicon crystalline material. The compensated silicon crystalline material includes a Czochralski silicon substrate.
    Type: Application
    Filed: November 2, 2023
    Publication date: May 8, 2025
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Jaroslav PJENCAK, Jan HYBL, Dusan POSTULKA, Juraj JARINA, David LYSACEK
  • Publication number: 20240071775
    Abstract: In an example, a method of manufacturing a semiconductor device includes providing a semiconductor substrate comprising an unpolished CZ silicon substrate, a substrate upper side, and a substrate lower side opposite to the substrate upper side. The method includes first annealing the semiconductor substrate at a first temperature in an inert environment for a first time. The method includes second annealing the semiconductor substrate at a second temperature in a wet oxidation environment for a second time. The first annealing dissolves inner wall oxide in bulk region voids and the second annealing fills the voids with semiconductor interstitials. In some examples, the CZ silicon substrate is provided from a CZ ingot grown in the presence of a magnetic field and using continuous counter-doping. The method provides, among other things, a CZ silicon substrate with reduced crystal originated particle (COP) defects, reduced oxygen concentration, and reduced radial resistivity variation.
    Type: Application
    Filed: August 24, 2022
    Publication date: February 29, 2024
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: David LYSACEK, Jan HYBL, Dusan POSTULKA, Juraj JARINA, Vit JANIREK, Alexandra SENKOVA