Patents by Inventor Dushyant Narayen

Dushyant Narayen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • System and method for compensating measured IDDQ values
    Patent number: 9007079
    Abstract: An IDDQ test system and method that, in one embodiment, includes 1) an empirical extraction subsystem operable to generate an IDDQ versus temperature model for a given semiconductor device design, 2) an automatic test equipment (ATE) test subsystem operable to obtain a measured IDDQ value (IDDQm) at a measured temperature (Tm) for a specific semiconductor device embodying the given semiconductor device design, the measured temperature (Tm) obtained within 5 seconds of obtaining the measured IDDQ value (IDDQm), and 3) a scaling subsystem operable to scale the measured IDDQ value (IDDQm) at the measured temperature (Tm) to a compensated IDDQ value (IDDQc) at a desired temperature (Td) using the IDDQ versus temperature model.
    Type: Grant
    Filed: November 2, 2012
    Date of Patent: April 14, 2015
    Assignee: Nvidia Corporation
    Inventors: Dushyant Narayen, Nerinder Singh, Gunaseelan Ponnuvel, Hemant Kumar, Luai Nasser, Craig Nishizaki
  • SYSTEM AND METHOD FOR COMPENSATING MEASURED IDDQ VALUES
    Publication number: 20140125364
    Abstract: An IDDQ test system and method that, in one embodiment,deg includes 1) an empirical extraction subsystem operable to generate an IDDQ versus temperature model for a given semiconductor device design, 2) an automatic test equipment (ATE) test subsystem operable to obtain a measured IDDQ value (IDDQm) at a measured temperature (Tm) for a specific semiconductor device embodying the given semiconductor device design, the measured temperature (Tm) obtained within 5 seconds of obtaining the measured IDDQ value (IDDQm), and 3) a scaling subsystem operable to scale the measured IDDQ value (IDDQm) at the measured temperature (Tm) to a compensated IDDQ value (IDDQc) at a desired temperature (Td) using the IDDQ versus temperature model.
    Type: Application
    Filed: November 2, 2012
    Publication date: May 8, 2014
    Applicant: NVIDIA CORPORATION
    Inventors: Dushyant Narayen, Nerinder Singh, Gunaseelan Ponnuvel, Hemant Kumar, Luai Nasser, Craig Nishizaki
  • Multi-layer staggered power bus layout design
    Patent number: 7067859
    Abstract: A bus layout design is provided which includes a first electrically conductive layer with a first bus and a second bus and a second electrically conductive layer with a first bus and a second bus. Vias are provided between the first electrically conductive layer and the second electrically conductive layer such that the first bus and the second bus of the first electrically conductive layer are electrically connected.
    Type: Grant
    Filed: August 26, 2003
    Date of Patent: June 27, 2006
    Assignee: LSI Logic Corporation
    Inventors: Matthew Russell, Dushyant Narayen, Dongyi Zhou
  • Multi-layer staggered power bus layout design
    Publication number: 20050046009
    Abstract: A bus layout design is provided which includes a first electrically conductive layer with a first bus and a second bus and a second electrically conductive layer with a first bus and a second bus. Vias are provided between the first electrically conductive layer and the second electrically conductive layer such that the first bus and the second bus of the first electrically conductive layer are electrically connected.
    Type: Application
    Filed: August 26, 2003
    Publication date: March 3, 2005
    Inventors: Matthew Russell, Dushyant Narayen, Dongyi Zhou