Patents by Inventor Dustin Feld

Dustin Feld has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and computer program for determining a placement of at least one circuit for a reconfigurable logic device
    Patent number: 10460062
    Abstract: Embodiments relate to a method and computer program for determining a placement of at least one circuit for a reconfigurable logic device. The method comprises obtaining (110) information related to the at least one circuit. The at least one circuit comprises a plurality of blocks and a plurality of connections between the plurality of blocks. The plurality of blocks comprise a plurality of logic blocks. The method further comprises calculating (120) a circuit graph based on the information related to the at least one circuit. The circuit graph comprises a plurality of nodes and a plurality of edges. The plurality of nodes represent at least a subset of the plurality of blocks of the at least one circuit and wherein the plurality of edges represent at least a subset of the plurality of connections between the plurality of blocks of the at least one circuit. The method further comprises determining (130) a force-directed layout of the circuit graph.
    Type: Grant
    Filed: December 11, 2017
    Date of Patent: October 29, 2019
    Assignee: Fraunhofer Gesellschaft zur Foerderung der angewandten Forschung e.V.
    Inventors: Dustin Feld, Thomas Soddemann
  • Method and Computer Program for Determining a Placement of at least one Circuit for a Reconfigurable Logic Device
    Publication number: 20180165400
    Abstract: Embodiments relate to a method and computer program for determining a placement of at least one circuit for a reconfigurable logic device. The method comprises obtaining (110) information related to the at least one circuit. The at least one circuit comprises a plurality of blocks and a plurality of connections between the plurality of blocks. The plurality of blocks comprise a plurality of logic blocks. The method further comprises calculating (120) a circuit graph based on the information related to the at least one circuit. The circuit graph comprises a plurality of nodes and a plurality of edges. The plurality of nodes represent at least a subset of the plurality of blocks of the at least one circuit and wherein the plurality of edges represent at least a subset of the plurality of connections between the plurality of blocks of the at least one circuit. The method further comprises determining (130) a force-directed layout of the circuit graph.
    Type: Application
    Filed: December 11, 2017
    Publication date: June 14, 2018
    Inventors: Dustin Feld, Thomas Soddemann