Patents by Inventor Dustin J. VanStee
Dustin J. VanStee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11158394Abstract: Embodiments relate methods and computer program products for performance testing of a solid state memory devices. The method includes operating a first solid state memory device for a period of time and capturing state information of the first solid state memory device after the period of time. The method also includes storing the state information in a control file and loading the control file onto a second solid state memory device. Once the control file has been loaded into the second solid state memory device the state information can be adapted to fix any issues due to physical variation. Performance testing can then be preformed on the second solid state memory device without preconditioning the second solid state memory device.Type: GrantFiled: April 2, 2020Date of Patent: October 26, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Thomas J. Griffin, Dustin J. VanStee
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Publication number: 20200234783Abstract: Embodiments relate methods and computer program products for performance testing of a solid state memory devices. The method includes operating a first solid state memory device for a period of time and capturing state information of the first solid state memory device after the period of time. The method also includes storing the state information in a control file and loading the control file onto a second solid state memory device. Once the control file has been loaded into the second solid state memory device the state information can be adapted to fix any issues due to physical variation. Performance testing can then be preformed on the second solid state memory device without preconditioning the second solid state memory device.Type: ApplicationFiled: April 2, 2020Publication date: July 23, 2020Inventors: Thomas J. Griffin, Dustin J. VanStee
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Patent number: 10658059Abstract: Embodiments relate methods and computer program products for performance testing of a solid state memory devices. The method includes operating a first solid state memory device for a period of time and capturing state information of the first solid state memory device after the period of time. The method also includes storing the state information in a control file and loading the control file onto a second solid state memory device. Once the control file has been loaded into the second solid state memory device the state information can be adapted to fix any issues due to physical variation. Performance testing can then be preformed on the second solid state memory device without preconditioning the second solid state memory device.Type: GrantFiled: October 14, 2016Date of Patent: May 19, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Thomas J. Griffin, Dustin J. VanStee
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Publication number: 20170032847Abstract: Embodiments relate methods and computer program products for performance testing of a solid state memory devices. The method includes operating a first solid state memory device for a period of time and capturing state information of the first solid state memory device after the period of time. The method also includes storing the state information in a control file and loading the control file onto a second solid state memory device. Once the control file has been loaded into the second solid state memory device the state information can be adapted to fix any issues due to physical variation. Performance testing can then be preformed on the second solid state memory device without preconditioning the second solid state memory device.Type: ApplicationFiled: October 14, 2016Publication date: February 2, 2017Inventors: Thomas J. Griffin, Dustin J. VanStee
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Patent number: 9524800Abstract: Embodiments relate methods and computer program products for performance testing of a solid state memory devices. The method includes operating a first solid state memory device for a period of time and capturing state information of the first solid state memory device after the period of time. The method also includes storing the state information in a control file and loading the control file onto a second solid state memory device. Once the control file has been loaded into the second solid state memory device the state information can be adapted to fix any issues due to physical variation. Performance testing can then be preformed on the second solid state memory device without preconditioning the second solid state memory device.Type: GrantFiled: September 26, 2012Date of Patent: December 20, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Thomas J. Griffin, Dustin J. VanStee
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Patent number: 9495287Abstract: Embodiments relate to solid state memory device including a storage array having a plurality of physical storage devices and the storage array includes a plurality of partitions. The solid state memory device also includes a controller comprising a plurality of mapping tables, wherein each of the plurality of mapping tables corresponds to one of the plurality of partitions. Each of the plurality of mapping tables is configured to store a physical location and a logical location of data stored in its corresponding partition.Type: GrantFiled: September 26, 2012Date of Patent: November 15, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Thomas J. Griffin, Dustin J. VanStee
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Patent number: 9495289Abstract: Embodiments relate to solid state memory device including a storage array having a plurality of physical storage devices and the storage array includes a plurality of partitions. The solid state memory device also includes a controller comprising a plurality of mapping tables, wherein each of the plurality of mapping tables corresponds to one of the plurality of partitions. Each of the plurality of mapping tables is configured to store a physical location and a logical location of data stored in its corresponding partition.Type: GrantFiled: December 4, 2013Date of Patent: November 15, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Thomas J. Griffin, Dustin J. VanStee
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Patent number: 9159458Abstract: A flash interface error injector for end-of-life testing of a flash-based array includes a plurality of error injection logic blocks that are implemented by one or more processors. Each of the plurality of error injection logic blocks corresponds with a respective flash channel. The flash injector also includes a bit flip probability logic that identifies one or more bits to be flipped.Type: GrantFiled: November 26, 2013Date of Patent: October 13, 2015Assignee: International Business Machines CorporationInventors: Thomas J. Griffin, Dustin J. Vanstee
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Patent number: 9047988Abstract: A flash interface error injector for end-of-life testing of a flash-based array includes a plurality of error injection logic blocks that are implemented by one or more processors. Each of the plurality of error injection logic blocks corresponds with a respective flash channel. The flash injector also includes a bit flip probability logic that identifies one or more bits to be flipped.Type: GrantFiled: November 20, 2012Date of Patent: June 2, 2015Assignee: International Business Machines CorporationInventors: Thomas J. Griffin, Dustin J. Vanstee
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Patent number: 9015537Abstract: According to exemplary embodiments, a system, is provided for bit error rate (BER)-based wear leveling in a solid state drive (SSD). A block-level BER value for a block in the SSD is determined. An adjusted PE cycle count for the block is incremented or decremented based on the block-level BER value. Wear leveling is then performed in the SSD based on the adjusted PE cycle count.Type: GrantFiled: December 10, 2013Date of Patent: April 21, 2015Assignee: International Business Machines CorporationInventors: Thomas J. Griffin, Dustin J. Vanstee
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Patent number: 9003068Abstract: A computer system having a host adapter is provided. The host adapter includes a primary port that follows a primary communication protocol. The primary port is connectable to at least one peripheral device. The host adapter includes a service port that follows a service communication protocol to monitor and send recovery commands to the peripheral device. The service port is decoupled and separate from the primary port and connectable to the at least one peripheral device.Type: GrantFiled: July 12, 2012Date of Patent: April 7, 2015Assignee: International Business Machines CorporationInventors: David D. Cadigan, Thomas J. Griffin, M. Dean Sciacca, Dustin J. VanStee
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Patent number: 8832506Abstract: According to exemplary embodiments, a system, method, and computer program product are provided for BER-based wear leveling in a SSD. A block-level BER value for a block in the SSD is determined. An adjusted PE cycle count for the block is incremented or decremented based on the block-level BER value. Wear leveling is then performed in the SSD based on the adjusted PE cycle count.Type: GrantFiled: January 20, 2012Date of Patent: September 9, 2014Assignee: International Business Machines CorporationInventors: Thomas J. Griffin, Dustin J. Vanstee
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Publication number: 20140143617Abstract: A flash interface error injector for end-of-life testing of a flash-based array includes a plurality of error injection logic blocks that are implemented by one or more processors. Each of the plurality of error injection logic blocks corresponds with a respective flash channel. The flash injector also includes a bit flip probability logic that identifies one or more bits to be flipped.Type: ApplicationFiled: November 20, 2012Publication date: May 22, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Thomas J. Griffin, Dustin J. Vanstee
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Publication number: 20140143618Abstract: A flash interface error injector for end-of-life testing of a flash-based array includes a plurality of error injection logic blocks that are implemented by one or more processors. Each of the plurality of error injection logic blocks corresponds with a respective flash channel. The flash injector also includes a bit flip probability logic that identifies one or more bits to be flipped.Type: ApplicationFiled: November 26, 2013Publication date: May 22, 2014Applicant: International Business Machines CorporationInventors: Thomas J. Griffin, Dustin J. Vanstee
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Publication number: 20140101499Abstract: According to exemplary embodiments, a system, is provided for bit error rate (BER)-based wear leveling in a solid state drive (SSD). A block-level BER value for a block in the SSD is determined. An adjusted PE cycle count for the block is incremented or decremented based on the block-level BER value. Wear leveling is then performed in the SSD based on the adjusted PE cycle count.Type: ApplicationFiled: December 10, 2013Publication date: April 10, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Thomas J. Griffin, Dustin J. Vanstee
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Publication number: 20140095773Abstract: Embodiments relate to solid state memory device including a storage array having a plurality of physical storage devices and the storage array includes a plurality of partitions. The solid state memory device also includes a controller comprising a plurality of mapping tables, wherein each of the plurality of mapping tables corresponds to one of the plurality of partitions. Each of the plurality of mapping tables is configured to store a physical location and a logical location of data stored in its corresponding partition.Type: ApplicationFiled: December 4, 2013Publication date: April 3, 2014Applicant: International Business Machines CorporationInventors: Thomas J. Griffin, Dustin J. VanStee
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Publication number: 20140088920Abstract: Embodiments relate methods and computer program products for performance testing of a solid state memory devices. The method includes operating a first solid state memory device for a period of time and capturing state information of the first solid state memory device after the period of time. The method also includes storing the state information in a control file and loading the control file onto a second solid state memory device. Once the control file has been loaded into the second solid state memory device the state information can be adapted to fix any issues due to physical variation. Performance testing can then be preformed on the second solid state memory device without preconditioning the second solid state memory device.Type: ApplicationFiled: September 26, 2012Publication date: March 27, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Thomas J. Griffin, Dustin J. VanStee
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Publication number: 20140019646Abstract: A computer system having a host adapter is provided. The host adapter includes a primary port that follows a primary communication protocol. The primary port is connectable to at least one peripheral device. The host adapter includes a service port that follows a service communication protocol to monitor and send recovery commands to the peripheral device. The service port is decoupled and separate from the primary port and connectable to the at least one peripheral device.Type: ApplicationFiled: July 12, 2012Publication date: January 16, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: David D. Cadigan, Thomas J. Griffin, M. Dean Sciacca, Dustin J. VanStee
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Patent number: 8627158Abstract: A mechanism is provided for a flash array test engine. The flash array test engine includes a circuit. The circuit is configured to generate test workloads in a test mode for testing a flash device array, where each of the test workloads includes specific addresses, data, and command patterns to be sent to the flash device array. The circuit is configured to accelerate wear in the flash device array, via the test workloads, at an accelerated rate relative to general system workloads that are not part of the test mode. The circuit is configured to vary a range of conditions for the flash device array to determine whether each of the conditions passes or fails and to store failure data and corresponding failure data address information for the flash device array.Type: GrantFiled: December 8, 2011Date of Patent: January 7, 2014Assignee: International Business Machines CorporationInventors: David D. Cadigan, Thomas J. Griffin, Archana Shetty, Gary A. Tressler, Dustin J. Vanstee
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Publication number: 20130339573Abstract: Embodiments relate to optimizing write performance of a flash device. Aspects include receiving a request to evict a plurality of pages from a main memory and determining a block size for the flash device. Aspects also include grouping the plurality of pages from the main memory into a move specification block, wherein a size of the move specification block is the block size and writing the move specification block to the flash device. The block size being determined based on one or more operational characteristics of the flash device.Type: ApplicationFiled: June 15, 2012Publication date: December 19, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Clark A. Anderson, Edward W. Chencinski, Jon S. Entwistle, Adrian C. Gerhard, Thomas J. Griffin, Charles E. Mari, Kenneth J. Oakes, Steven M. Partlow, Peter G. Sutton, Elpida Tzortzatos, Dustin J. VanStee