Patents by Inventor Dustin K. Slisher
Dustin K. Slisher has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9064972Abstract: A method of fabricating a semiconductor structure provided with a plurality of gated-diodes having a silicided anode (p-doped region) and cathode (n-doped region) and a high-K gate stack made of non-silicided gate material, the gated-diodes being adjacent to FETs, each of which having a silicided source, a silicided drain and a silicided HiK gate stack. The semiconductor structure eliminates a cap removal RIE in a gate first High-K metal gate flow from the region of the gated-diode. The lack of silicide and the presence of a nitride barrier on the gate of the diode are preferably made during the gate first process flow. The absence of the cap removal RIE is beneficial in that diffusions of the diode are not subjected to the cap removal RIE, which avoids damage and allows retaining its highly ideal junction characteristics.Type: GrantFiled: March 20, 2014Date of Patent: June 23, 2015Assignee: International Business Machines CorporationInventors: Anthony I. Chou, Arvind Kumar, Edward P. Maciejewski, Shreesh Narasimha, Dustin K. Slisher
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Patent number: 8912630Abstract: An integrated circuit (IC) and a method of making the same. In one embodiment, the IC includes: a substrate; an insulation layer over the substrate; a resistor over the insulation layer; a thermal gate over the resistor; and a heat sink connected to the thermal gate via a substrate contact, the heat sink adapted to receive thermal energy from the resistor via the thermal gate.Type: GrantFiled: April 11, 2012Date of Patent: December 16, 2014Assignee: International Business Machines CorporationInventors: Jed H. Rankin, Robert R. Robison, Dustin K. Slisher
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Publication number: 20140206160Abstract: A method of fabricating a semiconductor structure provided with a plurality of gated-diodes having a silicided anode (p-doped region) and cathode (n-doped region) and a high-K gate stack made of non-silicided gate material, the gated-diodes being adjacent to FETs, each of which having a silicided source, a silicided drain and a silicided HiK gate stack. The semiconductor structure eliminates a cap removal RIE in a gate first High-K metal gate flow from the region of the gated-diode. The lack of silicide and the presence of a nitride barrier on the gate of the diode are preferably made during the gate first process flow. The absence of the cap removal RIE is beneficial in that diffusions of the diode are not subjected to the cap removal RIE, which avoids damage and allows retaining its highly ideal junction characteristics.Type: ApplicationFiled: March 20, 2014Publication date: July 24, 2014Inventors: Anthony I. Chou, Arvind Kumar, Edward P. Maciejewski, Shreesh Narasimha, Dustin K. Slisher
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Patent number: 8779551Abstract: A semiconductor structure provided with a plurality of gated-diodes having a silicided anode (p-doped region) and cathode (n-doped region) and a high-K gate stack made of non-silicided gate material, the gated-diodes being adjacent to FETs, each of which having a silicided source, a silicided drain and a silicided HiK gate stack. The semiconductor structure eliminates a cap removal RIE in a gate first High-K metal gate flow from the region of the gated-diode. The lack of silicide and the presence of a nitride barrier on the gate of the diode are preferably made during the gate first process flow. The absence of the cap removal RIE is beneficial in that diffusions of the diode are not subjected to the cap removal RIE, which avoids damage and allows retaining its highly ideal junction characteristics.Type: GrantFiled: June 6, 2012Date of Patent: July 15, 2014Assignee: International Business Machines CorporationInventors: Anthony I. Chou, Arvind Kumar, Edward P. Maciejewski, Shreesh Narasimha, Dustin K. Slisher
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Patent number: 8652922Abstract: A method of forming a semiconductor structure includes forming a resistor on an insulator layer over a substrate and forming a trench in the resistor and into the substrate. The method also includes forming a liner on sidewalls of the trench and forming a core comprising a high thermal conductivity material in the trench and on the liner.Type: GrantFiled: January 18, 2011Date of Patent: February 18, 2014Assignee: International Business Machines CorporationInventors: Joseph M. Lukaitis, Jed H. Rankin, Robert R. Robison, Dustin K. Slisher, Timothy D. Sullivan
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Patent number: 8610217Abstract: Disclosed are embodiments of a self-protected electrostatic discharge field effect transistor (SPESDFET). In the SPESDFET embodiments, a resistance region is positioned laterally between two discrete sections of a deep source/drain region: a first section that is adjacent to the channel region and a second section that is contacted. The second section of the deep source/drain region is silicided, but the first section adjacent to the channel region and the resistance region are non-silicided. Additionally, the gate structure can be either silicided or non-silicided. With such a configuration, the disclosed SPESDFET provides robust ESD protection without consuming additional area and without altering the basic FET design (e.g., without increasing the distance between the deep source/drain regions and the channel region).Type: GrantFiled: December 14, 2010Date of Patent: December 17, 2013Assignee: International Business Machines CorporationInventors: Robert J. Gauthier, Jr., Mahender Kumar, Junjun Li, Dustin K. Slisher
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Publication number: 20130328124Abstract: A semiconductor structure provided with a plurality of gated-diodes having a silicided anode (p-doped region) and cathode (n-doped region) and a high-K gate stack made of non-silicided gate material, the gated-diodes being adjacent to FETs, each of which having a silicided source, a silicided drain and a silicided HiK gate stack. The semiconductor structure eliminates a cap removal RIE in a gate first High-K metal gate flow from the region of the gated-diode. The lack of silicide and the presence of a nitride barrier on the gate of the diode are preferably made during the gate first process flow. The absence of the cap removal RIE is beneficial in that diffusions of the diode are not subjected to the cap removal RIE, which avoids damage and allows retaining its highly ideal junction characteristics.Type: ApplicationFiled: June 6, 2012Publication date: December 12, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Anthony I. Chou, Arvind Kumar, Edward P. Maciejewski, Shreesh Narasimha, Dustin K. Slisher
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Publication number: 20130270678Abstract: An integrated circuit (IC) and a method of making the same. In one embodiment, the IC includes: a substrate; an insulation layer over the substrate; a resistor over the insulation layer; a thermal gate over the resistor; and a heat sink connected to the thermal gate via a substrate contact, the heat sink adapted to receive thermal energy from the resistor via the thermal gate.Type: ApplicationFiled: April 11, 2012Publication date: October 17, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jed H. Rankin, Robert R. Robison, Dustin K. Slisher
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Patent number: 8541864Abstract: A method of forming a semiconductor structure includes forming a resistor on an insulator layer over a substrate, and forming at least one dielectric layer over the resistor. The method also includes forming a substrate contact through the at least one dielectric layer, through the resistor, through the insulator layer, and into the substrate. The substrate contact comprises a high thermal conductivity material.Type: GrantFiled: August 17, 2012Date of Patent: September 24, 2013Assignee: International Business Machines CorporationInventors: Joseph M. Lukaitis, Jed H. Rankin, Robert R. Robison, Dustin K. Slisher, Timothy D. Sullivan
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Patent number: 8486796Abstract: A method of forming a semiconductor structure includes: forming a resistor over a substrate; forming at least one first contact in contact with the resistor; and forming at least one second contact in contact with the resistor. The resistor is structured and arranged such that current flows from the at least one first contact to the at least one second contact through a central portion of the resistor. The resistor includes at least one extension extending laterally outward from the central portion in a direction parallel to the current flow. The method includes sizing the at least one extension based on a thermal diffusion length of the resistor.Type: GrantFiled: November 19, 2010Date of Patent: July 16, 2013Assignee: International Business Machines CorporationInventors: David L. Harmon, Joseph M. Lukaitis, Stewart E. Rauch, III, Robert R. Robison, Dustin K. Slisher, Jeffrey H. Sloan, Timothy D. Sullivan, Kimball M. Watson
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Publication number: 20120313215Abstract: A method of forming a semiconductor structure includes forming a resistor on an insulator layer over a substrate, and forming at least one dielectric layer over the resistor. The method also includes forming a substrate contact through the at least one dielectric layer, through the resistor, through the insulator layer, and into the substrate. The substrate contact comprises a high thermal conductivity material.Type: ApplicationFiled: August 17, 2012Publication date: December 13, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Joseph M. LUKAITIS, Jed H. RANKIN, Robert R. ROBISON, Dustin K. SLISHER, Timothy D. SULLIVAN
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Patent number: 8298904Abstract: A method of forming a semiconductor structure includes forming a resistor on an insulator layer over a substrate, and forming at least one dielectric layer over the resistor. The method also includes forming a substrate contact through the at least one dielectric layer, through the resistor, through the insulator layer, and into the substrate. The substrate contact comprises a high thermal conductivity material.Type: GrantFiled: January 18, 2011Date of Patent: October 30, 2012Assignee: International Business Machines CorporationInventors: Joseph M. Lukaitis, Jed H. Rankin, Robert R. Robison, Dustin K. Slisher, Timothy D. Sullivan
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Patent number: 8234001Abstract: A method of analyzing production steps includes inputting application data associated with a production process having a plurality of process steps into a memory with each of the plurality of process steps including a plurality of tools. The method also includes loading process data associated with one of the plurality of process steps into the memory, performing a tool commonality analysis on each of the tools associated with the at least one of the plurality of process steps, identifying all tool-to-tool differences for the at least one of the plurality of process steps, performing a tool stratification analysis to identify one of the plurality of tools that provides the largest variance contribution to the at least one of the plurality of process steps, and stopping the one of the plurality of tools that provides the largest variance contribution to the at least one of the plurality of process steps.Type: GrantFiled: September 28, 2009Date of Patent: July 31, 2012Assignee: International Business Machines CorporationInventors: James Rice, Dustin K. Slisher, Yunsheng Song
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Publication number: 20120181663Abstract: A method of forming a semiconductor structure includes forming a resistor on an insulator layer over a substrate and forming a trench in the resistor and into the substrate. The method also includes forming a liner on sidewalls of the trench and forming a core comprising a high thermal conductivity material in the trench and on the liner.Type: ApplicationFiled: January 18, 2011Publication date: July 19, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Joseph M. LUKAITIS, Jed H. RANKIN, Robert R. ROBISON, Dustin K. SLISHER, Timothy D. SULLIVAN
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Publication number: 20120184080Abstract: A method of forming a semiconductor structure includes forming a resistor on an insulator layer over a substrate, and forming at least one dielectric layer over the resistor. The method also includes forming a substrate contact through the at least one dielectric layer, through the resistor, through the insulator layer, and into the substrate. The substrate contact comprises a high thermal conductivity material.Type: ApplicationFiled: January 18, 2011Publication date: July 19, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Joseph M. LUKAITIS, Jed H. RANKIN, Robert R. ROBISON, Dustin K. SLISHER, Timothy D. SULLIVAN
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Publication number: 20120146150Abstract: Disclosed are embodiments of a self-protected electrostatic discharge field effect transistor (SPESDFET). In the SPESDFET embodiments, a resistance region is positioned laterally between two discrete sections of a deep source/drain region: a first section that is adjacent to the channel region and a second section that is contacted. The second section of the deep source/drain region is silicided, but the first section adjacent to the channel region and the resistance region are non-silicided. Additionally, the gate structure can be either silicided or non-silicided. With such a configuration, the disclosed SPESDFET provides robust ESD protection without consuming additional area and without altering the basic FET design (e.g., without increasing the distance between the deep source/drain regions and the channel region).Type: ApplicationFiled: December 14, 2010Publication date: June 14, 2012Applicant: International Business Machines CorporationInventors: Robert J. Gauthier, JR., Mahender Kumar, Junjun Li, Dustin K. Slisher
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Publication number: 20120126370Abstract: A method of forming a semiconductor structure includes: forming a resistor over a substrate; forming at least one first contact in contact with the resistor; and forming at least one second contact in contact with the resistor. The resistor is structured and arranged such that current flows from the at least one first contact to the at least one second contact through a central portion of the resistor. The resistor includes at least one extension extending laterally outward from the central portion in a direction parallel to the current flow. The method includes sizing the at least one extension based on a thermal diffusion length of the resistor.Type: ApplicationFiled: November 19, 2010Publication date: May 24, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: David L. HARMON, Joseph M. LUKAITIS, Stewart E. RAUCH, III, Robert R. ROBISON, Dustin K. SLISHER, Jeffrey H. SLOAN, Timothy D. SULLIVAN, Kimball M. WATSON
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Publication number: 20110077765Abstract: A method of analyzing production steps includes inputting application data associated with a production process having a plurality of process steps into a memory with each of the plurality of process steps including a plurality of tools. The method also includes loading process data associated with one of the plurality of process steps into the memory, performing a tool commonality analysis on each of the tools associated with the at least one of the plurality of process steps, identifying all tool-to-tool differences for the at least one of the plurality of process steps, performing a tool stratification analysis to identify one of the plurality of tools that provides the largest variance contribution to the at least one of the plurality of process steps, and stopping the one of the plurality of tools that provides the largest variance contribution to the at least one of the plurality of process steps.Type: ApplicationFiled: September 28, 2009Publication date: March 31, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: James Rice, Dustin K. Slisher, Yunsheng Song
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Patent number: 7381577Abstract: A method and apparatus for identifying defective partially manufactured semiconductor wafers in a manufacturing line is described, wherein defects caused by silicon erosion created by over-etching the wafer can be detected. The method described herein is based on an in-line test of selected structures, such as FETs, located in the kerfs that surround the integrated circuit chips. Leakage current between the gate and the source-drain region is measured at FETs in each kerf. Based on the measurement, a leakage current map is created and compared to a standard map. In accordance with this comparison and to the distribution of patterns of leakage currents, it is determined whether or not the wafer is defective. This determination is performed in the kerfs after formation of the gate and source-drain regions, and prior to the wafer being completed. By detecting defective wafers at an early stage, considerable manufacturing resources are saved.Type: GrantFiled: April 19, 2005Date of Patent: June 3, 2008Assignee: International Business Machines CorporationInventor: Dustin K. Slisher