Abstract: A composition comprising an active material and method for forming the same. The method for manufacturing an active material can include preparing one or more polychalcogen containing liquids, preparing a graphene nanoplatelet containing liquid, preparing an organic acid liquid, and mixing the various liquids, which can be in the form of liquids, suspensions or emulsions, to form a mixture. Additionally, the method can include filtering the mixture to produce a filtrate, and drying the filtrate to produce the active material.

Abstract: For optimizing expansion devices on a computer expansion bus based on real-time flow control data, a system, apparatus, method, and computer program product are disclosed. The apparatus includes a configuration module that initializes a plurality of expansion bus registers, each expansion bus register associated with one of the plurality of expansion bus slots, a packet module that monitors flow control packets on the expansion bus, a flow control module that calculates flow control data from the flow control packets, the flow control data relating to the plurality of expansion devices, and a register module that writes flow control data to the plurality of expansion bus registers. The apparatus may further includes an optimization module that calculates an arrangement of the plurality of expansion devices, based on the flow control data, to maximize expansion bus throughput.

Abstract: A system includes a CPU including a primary address decode logic module (PADLM) and a plurality of diagnostic registers, wherein the PADLM includes address bus inputs, and an enable input port. The system further includes a data flip-flop having a data input coupled to a master enable signal line, a set input coupled to an interrupt signal line, an output coupled to the enable input port of the PADLM, and a clock input. Still further, the system includes an address decode logic module having a memory address input and an output indicating whether the memory address is within a predetermined address range of the diagnostic registers, wherein the output of the address decode logic module is coupled to the clock input. Memory mapping is enabled in response to receiving an interrupt signal and determining that the memory address is within a predetermined range of memory addresses for diagnostic registers.

Abstract: A starting logical lane of a logical bus is set to the first or last physical lane of a physical bus. A width of a logical bus is set to half the number of physical lanes. If a fault is absent in the logical bus, the starting logical lane is set to the other of the first and last physical lanes. The width is repeatingly divided by two until it is equal to one lane or the fault is not present in the logical bus. When the fault is absent in the logical bus and the width is greater than one lane, the fault is present within a range of the physical lanes encompassing a contiguous number of the physical lanes and the first or last physical lane.

Abstract: A starting logical lane of a logical bus is set to the first or last physical lane of a physical bus. A width of a logical bus is set to half the number of physical lanes. If a fault is absent in the logical bus, the starting logical lane is set to the other of the first and last physical lanes. The width is repeatingly divided by two until it is equal to one lane or the fault is not present in the logical bus. When the fault is absent in the logical bus and the width is greater than one lane, the fault is present within a range of the physical lanes encompassing a contiguous number of the physical lanes and the first or last physical lane.

Abstract: A system includes a CPU including a primary address decode logic module (PADLM) and a plurality of diagnostic registers, wherein the PADLM includes address bus inputs, and an enable input port. The system further includes a data flip-flop having a data input coupled to a master enable signal line, a set input coupled to an interrupt signal line, an output coupled to the enable input port of the PADLM, and a clock input. Still further, the system includes an address decode logic module having a memory address input and an output indicating whether the memory address is within a predetermined address range of the diagnostic registers, wherein the output of the address decode logic module is coupled to the clock input. Memory mapping is enabled in response to receiving an interrupt signal and determining that the memory address is within a predetermined range of memory addresses for diagnostic registers.

Abstract: For optimizing expansion devices on a computer expansion bus based on real-time flow control data, a system, apparatus, method, and computer program product are disclosed. The apparatus includes a configuration module that initializes a plurality of expansion bus registers, each expansion bus register associated with one of the plurality of expansion bus slots, a packet module that monitors flow control packets on the expansion bus, a flow control module that calculates flow control data from the flow control packets, the flow control data relating to the plurality of expansion devices, and a register module that writes flow control data to the plurality of expansion bus registers. The apparatus may further includes an optimization module that calculates an arrangement of the plurality of expansion devices, based on the flow control data, to maximize expansion bus throughput.