Abstract: A memory built-in self test (MBIST) apparatus and method for testing dynamic random access memory (DRAM) arrays, the DRAM arrays in communication with a memory interface device that includes interface logic and mainline chip logic. The MBIST apparatus includes a finite state machine including a command generator and logic for incrementing data and addresses under test and a command scheduler in communication with the finite state machine. The command scheduler includes resource allocation logic for spacing commands to memory dynamically utilizing DRAM timing parameters. The MBIST apparatus also includes a test memory storing subtests of an MBIST test. Each of the subtests provides a full pass through a configured address range. The MBIST apparatus further includes a subtest pointer in communication with the test memory and the finite state machine. The finite state machine implements subtest sequencing of each of the subtests via the subtest pointer.

Abstract: A memory system including a plurality of delay lines and a processor in communication with the delay lines. The delay lines are in communication with a bus attached to a memory device. The bus includes a plurality of wires and each of the delay lines corresponds to on of the plurality of wires. The processor receives a plurality of data bits and a data strobe via the wires on the bus. Each of the data bits includes data eye. The process also automatically calibrates the target data eye of each of the data bits and corresponds to the target data eye. In addition, the processor centers the data strobe over the target data eye.

Abstract: A synchronous input to output protocol translator supporting multiple reference oscillator frequencies and fixed latency data computation and chip crossing circuits enables implementation of a method for delaying osc2 relative to osc1 in a configurable way to provide a constant, minimal Tptcc over a range of refosc frequencies between circuits for data transferred. It requires that the data transferred from a register R1 be sent over multiple wires via configurable delay circuitry for osc2, capture circuitry at the input to R2, and a circuit to transfer a synchronizing signal from a non-delayed clock domain to a delayed clock domain. Relative to osc1, osc2 is a delayed, synchronous clock.