Abstract: A display module, a display drive circuit, and an electronic device. The display module includes a display and at least one driver group. The display includes M rows of sub-pixels arranged in a matrix form. Each sub-pixel includes a driving transistor, a first reset transistor, a first capacitor, and a light emitting device. Each driver group includes M selecting circuits. The Nth selecting circuit is coupled to a second node of a first reset transistor in the Nth row of sub-pixels. The selecting circuit is configured to output a second initial voltage Vint2 to the second node, and is configured to output a first initial voltage Vint1 to the second node, where |Vint2|>|Vint1|.

Abstract: This application provides an electronic device, to reduce a probability that a screen stalling phenomenon. A timing control unit sends one first pulse of a tearing effect signal every a first preset time T1. The timing control unit sends S second pulses of the tearing effect signal when a transceiver unit does not receive an Nth frame of display data within a preset time. The processing unit receives the Nth frame of display data in the (N+1)th frame, and controls, based on the Nth frame of display data, the display to display an Nth frame of image.

Abstract: This application provide a display module and an electronic device, to reduce a probability of a display flicker. A display module includes a display, a display driver circuit, and at least one driver group; the display includes M rows of sub pixels; each driver group includes M gating circuits; an Nth gating circuit is configured to: receive a first initial voltage Vinit1 and a second initial voltage Vinit2 from the display driver circuit, output the second initial voltage Vinit2 to a second electrode of a first reset transistor and a first electrode of a voltage modulation transistor, and output the first initial voltage Vinit1 to the second electrode of the first reset transistor and the first electrode of the voltage modulation transistor.

Abstract: An electronic device includes a host controller. The host controller splits a to-be-displayed image into at least two sub images, where each sub image and an adjacent sub image thereof include at least one column of overlapping image pixels. The host controller sends the at least two sub images to at least two display drive circuits, so that the at least two display drive circuits can jointly drive a display screen to display the to-be-displayed image in a sub pixel rendering (SPR) manner.

Abstract: This application provide a display module and an electronic device, to reduce a probability of a display flicker. A display module includes a display, a display driver circuit, and at least one driver group; the display includes M rows of sub pixels; each driver group includes M gating circuits; an Nth gating circuit is configured to: receive a first initial voltage Vinit1 and a second initial voltage Vinit2 from the display driver circuit, output the second initial voltage Vinit2 to a second electrode of a first reset transistor and a first electrode of a voltage modulation transistor, and output the first initial voltage Vinit1 to the second electrode of the first reset transistor and the first electrode of the voltage modulation transistor.

Abstract: This application provides an electronic device, to reduce a probability that a screen stalling phenomenon. A timing control unit sends one first pulse of a tearing effect signal every a first preset time T1. The timing control unit sends S second pulses of the tearing effect signal when a transceiver unit does not receive an Nth frame of display data within a preset time. The processing unit receives the Nth frame of display data in the (N+1)th frame, and controls, based on the Nth frame of display data, the display to display an Nth frame of image.

Abstract: An electronic device includes a display screen, where the display screen includes a first display region and a second display region, and a display driving system including a first emission (EM) signal output end configured to send a first EM signal to the display screen, where the display driving system further includes a second EM signal output end configured to send a second EM signal to the display screen, where the first EM signal controls the first display region to display an image in a first time period, and the second EM signal controls the second display region not to display an image in the first time period.

Abstract: An electronic device includes a display including a first display area and a second display area. The electronic device further includes a main controller configured to send a first clock signal separately to a first display driver circuit and a second display driver circuit. The first display driver circuit is configured to receive the first clock signal and to output a first GOA clock signal to the display. The first GOA clock signal is generated based on the first clock signal. The second display driver circuit is configured to receive the first clock signal, and is further configured to output a second GOA clock signal to the display. The second GOA clock signal is generated based on the first clock signal.

Abstract: A display module, a display drive circuit, and an electronic device. The display module includes a display and at least one driver group. The display includes M rows of sub-pixels arranged in a matrix form. Each sub-pixel includes a driving transistor, a first reset transistor, a first capacitor, and a light emitting device. Each driver group includes M selecting circuits. The Nth selecting circuit is coupled to a second node of a first reset transistor in the Nth row of sub-pixels. The selecting circuit is configured to output a second initial voltage Vint2 to the second node, and is configured to output a first initial voltage Vint1 to the second node, where |Vint2|>|Vint1|.

Abstract: An electronic device includes a host controller. The host controller splits a to-be-displayed image into at least two sub images, where each sub image and an adjacent sub image thereof include at least one column of overlapping image pixels. The host controller sends the at least two sub images to at least two display drive circuits, so that the at least two display drive circuits can jointly drive a display screen to display the to-be-displayed image in a sub pixel rendering (SPR) manner.

Abstract: An electronic device includes a display including a first display area and a second display area. The electronic device further includes a main controller configured to send a first clock signal separately to a first display driver circuit and a second display driver circuit. The first display driver circuit is configured to receive the first clock signal, and to output a first GOA clock signal to the display. The first GOA clock signal is generated based on the first clock signal. The second display driver circuit is configured to receive the first clock signal, and is further configured to output a second GOA clock signal to the display. The second GOA clock signal is generated based on the first clock signal.

Abstract: An electronic device includes a display screen, where the display screen includes a first display region and a second display region, and a display driving system including a first emission (EM) signal output end configured to send a first EM signal to the display screen, where the display driving system further includes a second EM signal output end configured to send a second EM signal to the display screen, where the first EM signal controls the first display region to display an image in a first time period, and the second EM signal controls the second display region not to display an image in the first time period.

Abstract: Methods and apparatuses for controlling brightness of a display are disclosed in the present disclosure. One method includes: determining a first brightness value of a display at a current brightness adjustment level; determining, based on a gamma correction lookup table, a first input grayscale value corresponding to the first brightness value, wherein the gamma correction lookup table comprises a gamma correction relationship between a brightness value of the display and an initial input grayscale value of the display at a predetermined brightness adjustment levels; and controlling an output brightness value of the display based on the first input grayscale value.

Abstract: A gate driving circuit includes a first connection controller, a first driving group configured to receive a start signal from a first signal end of a display driver and a second driving group configured to receive an active signal from a fifth end of the first connection controller. A first end of the first connection controller is configured to receive an active signal from the first driving group. A second end of the first connection controller is configured to receive a cascade gating signal from a second signal end of the display driver. A third end of the first connection controller is configured to receive a split-screen gating signal from a third signal end of the display driver. A fourth end of the first connection controller is configured to receive a split-screen display signal from a fourth signal end of the display driver.

Abstract: Methods and apparatuses for controlling brightness of a display are disclosed in the present disclosure. One method includes: determining a first brightness value of a display at a current brightness adjustment level; determining, based on a gamma correction lookup table, a first input grayscale value corresponding to the first brightness value, wherein the gamma correction lookup table comprises a gamma correction relationship between a brightness value of the display and an initial input grayscale value of the display at a predetermined brightness adjustment levels; and controlling an output brightness value of the display based on the first input grayscale value.

Abstract: A display drive integrated circuit includes a frame buffer, an output selector and a timing controller. The output selector selectively outputs one of image data read from the frame buffer and image data transmitted from a source external to the display drive integrated circuit. The timing controller controls output of the image data read from the frame buffer to the display panel in a self-refresh mode, and controls internal display timing to track external display timing when the display drive integrated circuit exits from the self-refresh mode to control the output selector to output the image data transmitted from the source to the display panel when the internal display timing is synchronized to the external display timing.

Abstract: A display drive integrated circuit includes a frame buffer, an output selector and a timing controller. The output selector selectively outputs one of image data read from the frame buffer and image data transmitted from a source external to the display drive integrated circuit. The timing controller controls output of the image data read from the frame buffer to the display panel in a self-refresh mode, and controls internal display timing to track external display timing when the display drive integrated circuit exits from the self-refresh mode to control the output selector to output the image data transmitted from the source to the display panel when the internal display timing is synchronized to the external display timing.