Abstract: A computer implemented method, apparatus and computer program product for extending test coverage in a simulated multiple core integrated circuit. The simulator applies at a first time a first test vector on the simulated multiple core integrated circuit, the first test vector having a duration. The simulator may also apply a second test vector at a second time before the duration but substantially after the first time. The simulator can collect a response from the multiple core integrated circuit based on the first test vector and the second test vector.

Abstract: A computer implemented method, apparatus and computer program product for extending test coverage in a simulated multiple core integrated circuit. The simulator applies at a first time a first test vector on the simulated multiple core integrated circuit, the first test vector having a duration. The simulator may also apply a second test vector at a second time before the duration but substantially after the first time. The simulator can collect a response from the multiple core integrated circuit based on the first test vector and the second test vector.

Abstract: A homograph filter and method which increase the probability that homographs are pronounced correctly in a speech synthesis system utilizes a filter engine operating in conjunction with a set of rules. The filter engine parses a textual sentence to extract any present homographs and applies a correct set of rules to the homograph, based on an optimal search algorithm. The engine then carries out any appropriate substitution of phonetic data. Rules are primarily based on syntactic analisis, based on a priori knowledge of how each homograph is used. The rule set is classified into different categories in order to optimize the search algorithm and to allow the rules to be modified and updated incrementally without effecting the engine construction and/or performance. The search algorithm utilizes syntactic analysis to achieve optimum results.

Abstract: A computer system having a peripheral bus and a digital signal processor (DSP) local bus interfacing to the peripheral bus via an extended bus interface circuit (EBIC). The DSP local bus is configured such that devices, which are typically two or more DSPs, electrically connected to the DSP local bus may transfer data to other devices connected to the DSP local bus regardless of data transfer activity of the peripheral bus. Moreover, as seen from the peripheral bus, the devices connected to the DSP local bus have the same arbitration level. However, as seen from the DSP local bus, each device connected to the DSP local bus has a unique arbitration level determined by the priority of the tasks executing on the respective devices, as determined by a DSP operating system.

Abstract: This invention relates to personal computers, and to the handling of input/output signals exchanged between a microprocessor included within a personal computer and devices remote from the microprocessor. In addition to the microprocessor and a system board mounting the microprocessor, a personal computer in accordance with this invention has an input/output signal processing circuit for performing logical operations on digital signals passing to and from the microprocessor and preparing such signals for operative communication between the microprocessor and devices remote from the microprocessor, a second circuit board for mounting the circuit, a board connector mounting the second circuit board on the system board, an input/output connector for passing signals to and from the circuit for receipt from and delivery to devices remote from the microprocessor, and a signal communicating member extending between the circuit and the input/output connector for operatively communicating signals therebetween.