Patents by Inventor Duy Thanh Nguyen

Duy Thanh Nguyen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • ELECTRONIC DEVICE INCLUDING NEURAL PROCESSING UNIT SUPPORTING DIFFERENT DATA TYPES AND METHOD FOR CONTROLLING THE SAME
    Publication number: 20230123312
    Abstract: An operational circuit may include a combiner to combine, based on a request for multiplication of integer numbers different from floating-point numbers, a first integer number and a second integer number. The operational circuit may include a multiplier including first and second ports. A third integer number may be inputted to the first port, and a fourth integer number indicating a combination of the first integer number and the second integer number may inputted to the second port. The operational circuit may include a converter to output, based on a fifth integer number indicating a multiplication of the third integer number and the fourth integer number from a third port of the multiplier, a sixth integer number indicating a multiplication of the first integer number and the third integer number, and a seventh integer number indicating a multiplication of the second integer number and the third integer number.
    Type: Application
    Filed: July 29, 2022
    Publication date: April 20, 2023
    Inventors: Duy Thanh NGUYEN, Jin CHOI
  • Memory controller storing data in approximate memory device based on priority-based ECC, non-transitory computer-readable medium storing program code, and electronic device comprising approximate memory device and memory controller
    Patent number: 11144386
    Abstract: A memory controller includes an error correction circuit that converts some bits of first data into parity bits for an error correction operation and generates second data including remaining bits of the first data and the parity bits replaced from the some bits, and a physical layer that transmits the second data instead of the first data to a memory device.
    Type: Grant
    Filed: October 23, 2019
    Date of Patent: October 12, 2021
    Assignee: UNIVERSITY-INDUSTRY COOPERATION GROUP OF KYUNG HEE UNIVERSITY
    Inventors: Ik Joon Chang, Duy Thanh Nguyen
  • Approximate memory architecture and data processing apparatus having the same
    Patent number: 10916291
    Abstract: The provided is a method of controlling a dynamic random-access memory (DRAM) device comprising: storing a plurality of pieces of data consisting of a plurality of bits in a memory in a transposed manner; setting at least one refresh period for each of a plurality of rows constituting the memory; and performing a refresh operation of the memory on the basis of the set refresh period.
    Type: Grant
    Filed: August 13, 2019
    Date of Patent: February 9, 2021
    Assignees: SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION, UNIVERSITY-INDUSTRY COOPERATION GROUP OF KYUNG LEE UNIVERSITY
    Inventors: Hyuk Jae Lee, Hyun Kim, Duy Thanh Nguyen, Bo Yeal Kim, Ik Joon Chang
  • APPROXIMATE MEMORY ARCHITECTURE AND DATA PROCESSING APPARATUS HAVING THE SAME
    Publication number: 20200381039
    Abstract: The provided is a method of controlling a dynamic random-access memory (DRAM) device comprising: storing a plurality of pieces of data consisting of a plurality of bits in a memory in a transposed manner; setting at least one refresh period for each of a plurality of rows constituting the memory; and performing a refresh operation of the memory on the basis of the set refresh period.
    Type: Application
    Filed: August 13, 2019
    Publication date: December 3, 2020
    Inventors: Hyuk Jae LEE, Hyun KIM, Duy Thanh NGUYEN, Bo Yeal KIM, Ik Joon CHANG
  • MEMORY CONTROLLER STORING DATA IN APPROXIMATE MEMORY DEVICE BASED ON PRIORITY-BASED ECC, NON-TRANSITORY COMPUTER-READABLE MEDIUM STORING PROGRAM CODE, AND ELECTRONIC DEVICE COMPRISING APPROXIMATE MEMORY DEVICE AND MEMORY CONTROLLER
    Publication number: 20200341840
    Abstract: A memory controller includes an error correction circuit that converts some bits of first data into parity bits for an error correction operation and generates second data including remaining bits of the first data and the parity bits replaced from the some bits, and a physical layer that transmits the second data instead of the first data to a memory device.
    Type: Application
    Filed: October 23, 2019
    Publication date: October 29, 2020
    Applicant: University-Industry Cooperation Group of Kyung Hee University
    Inventors: Ik Joon Chang, Duy Thanh Nguyen