Patents by Inventor Dwayne S. Reichl
Dwayne S. Reichl has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20150187873Abstract: A power device includes an active region and a termination region surrounding the active region. A plurality of pillars of first and second conductivity type are alternately arranged in each of the active and termination regions. The pillars of first conductivity type in the active and termination regions have substantially the same width, and the pillars of second conductivity type in the active region have a smaller width than the pillars of second conductivity type in the termination region so that a charge balance condition in each of the active and termination regions results in a higher breakdown voltage in the termination region than in the active region.Type: ApplicationFiled: January 5, 2015Publication date: July 2, 2015Inventors: Joseph A. Yedinak, Jaegil Lee, Hocheol Jang, Chongman Yun, Praveen Muraleedharan Shenoy, Christopher L. Rexer, Changwook Kim, Jonghun Lee, Jasong M. Higgs, Dwayne S. Reichl, Joelle Sharp, Qi Wang, Yongsub Kim, Jungkil Lee, Mark L. Rinehimer, Jinyoung Jung
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Publication number: 20150069567Abstract: A power device includes a semiconductor region which in turn includes a plurality of alternately arranged pillars of first and second conductivity type. Each of the plurality of pillars of second conductivity type further includes a plurality of implant regions of the second conductivity type arranged on top of one another along the depth of pillars of second conductivity type, and a trench portion filled with semiconductor material of the second conductivity type directly above the plurality of implant regions of second conductivity type.Type: ApplicationFiled: September 19, 2014Publication date: March 12, 2015Inventors: Joseph A. Yedinak, Christopher L. Rexer, Mark L. Rinehimer, Praveen Muraleedharan Shenoy, Jaegil Lee, Hamza Yilmaz, Chongman Yun, Dwayne S. Reichl, James Pan, Rodney S. Ridley, Harold Heidenreich
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Patent number: 8928077Abstract: In one general aspect, a power device includes an active region having a plurality of pillars of a first conductivity type alternately arranged with a plurality of pillars of a second conductivity type where the plurality of pillars of the second conductivity type in the active region each have substantially the same width. The power device includes a termination region surrounding at least a portion of the active region and having a plurality of pillars of the first conductivity type alternately arranged with a plurality of pillars of the second conductivity type where the plurality of pillars of the second conductivity type in the active region each have substantially the same width and are smaller than each width of the pillars of the second conductivity type in the termination region. The power device includes a transition region disposed between the active region and the termination region.Type: GrantFiled: September 19, 2008Date of Patent: January 6, 2015Assignee: Fairchild Semiconductor CorporationInventors: JaeGil Lee, Chongman Yun, Hocheol Jang, Christopher L. Rexer, Praveen Muraleedharan Shenoy, Dwayne S. Reichl, Joseph A. Yedinak
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Publication number: 20140264434Abstract: In a general aspect, an apparatus can include an insulated-gate bipolar transistor (IGBT) device disposed in a semiconductor region. The apparatus can further include a plurality of clamping diodes. The plurality of clamping diodes can be coupled in series between a collector terminal of the IGBT device and a gate terminal of the IGBT device. The apparatus can also include a gate pad disposed over at least a portion of the plurality of clamping diodes. The at least a portion of the plurality of clamping diodes can be configured, during operation of the apparatus, to have a voltage of at least 120 V applied across them.Type: ApplicationFiled: March 14, 2014Publication date: September 18, 2014Applicant: Fairchild Semiconductor CorporationInventors: Joseph A. YEDINAK, Dwayne S. REICHL, Donald Burton
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Patent number: 8836028Abstract: In a general aspect, a power device can include at least one N-type epitaxial layer disposed on a substrate and a plurality of N-pillars and P-pillars that define alternating P-N-pillars in the at least one N-type epitaxial layer. The power device can also include an active region and a termination region, where the termination region surrounds the active region. The alternating P-N-pillars can be disposed in both the active region and the termination region, where the termination region can include a predetermined number of floating P-pillars.Type: GrantFiled: April 27, 2011Date of Patent: September 16, 2014Assignee: Fairchild Semiconductor CorporationInventors: Joseph A. Yedinak, Mark L. Rinehimer, Praveen Muraleedharan Shenoy, Jaegil Lee, Dwayne S. Reichl, Harold Heidenreich
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Publication number: 20120273916Abstract: A power device includes a semiconductor region which in turn includes a plurality of alternately arranged pillars of first and second conductivity type. Each of the plurality of pillars of second conductivity type further includes a plurality of implant regions of the second conductivity type arranged on top of one another along the depth of pillars of second conductivity type, and a trench portion filled with semiconductor material of the second conductivity type directly above the plurality of implant regions of second conductivity type.Type: ApplicationFiled: April 27, 2011Publication date: November 1, 2012Inventors: Joseph A. Yedinak, Christopher L. Rexer, Mark L. Rinehimer, Praveen Muraleedharan Shenoy, Jaegil Lee, Hamza Yilmaz, Chongman Yun, Dwayne S. Reichl, James Pan, Rodney S. Ridley, SR., Harold Heidenreich
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Publication number: 20120273884Abstract: A power device includes a semiconductor region which in turn includes a plurality of alternately arranged pillars of first and second conductivity type. Each of the plurality of pillars of second conductivity type further includes a plurality of implant regions of the second conductivity type arranged on top of one another along the depth of pillars of second conductivity type, and a trench portion filled with semiconductor material of the second conductivity type directly above the plurality of implant regions of second conductivity type.Type: ApplicationFiled: April 27, 2011Publication date: November 1, 2012Inventors: Joseph A. Yedinak, Christopher L. Rexer, Mark L. Rinehimer, Praveen Muraleedharan Shenoy, Jaegil Lee, Hamza Yilmaz, Chongman Yun, Dwayne S. Reichl, James Pan, Rodney S. Ridley, SR., Harold Heidenreich
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Patent number: 7230313Abstract: An integrated circuit includes a die having a device layer. An insulating layer is disposed over the device layer. A die street defines the outermost bounds of the die. A voltage divider network including a plurality of resistive elements derives a plurality of predetermined bias voltages. A field plate termination includes a plurality of field plates disposed on the oxide layer and are laterally spaced apart relative to each other and relative to the die street. Each of the plurality of field plates is electrically connected to a corresponding bias voltage. The bias voltage applied to a given field plate is determined by and increases with the proximity of that field plate relative to the die street.Type: GrantFiled: October 9, 2003Date of Patent: June 12, 2007Assignee: Fairchild Semiconductor CorporationInventors: Joseph A. Yedinak, Dwayne S. Reichl, Bernard J. Czeck, Douglas J. Lange
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Patent number: 7118951Abstract: An integrated circuit die includes an active area having source dopants and contacts. An active area metal layer overlies the active area. A sense area is disposed on the die. A sense area metal layer overlies the sense area. A plurality of polysilicon gate stripes, polysilicon openings, and body stripes are disposed on the die, and extend in a continuous and uninterrupted manner from the active area into the sense area. A first region from which source dopants and contacts have been excluded surrounds a periphery of the sense area. An etched region is disposed over the first region, thereby separating and electrically isolating the sense area metal layer from the active area metal layer.Type: GrantFiled: May 17, 2005Date of Patent: October 10, 2006Assignee: Fairchild Semiconductor CorporationInventors: Joseph A. Yedinak, Dwayne S. Reichl, Douglas J. Lange
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Patent number: 6906362Abstract: An integrated circuit die includes an active area having source dopants and contacts. An active area metal layer overlies the active area. A sense area is disposed on the die. A sense area metal layer overlies the sense area. A plurality of polysilicon gate stripes, polysilicon openings, and body stripes are disposed on the die, and extend in a continuous and uninterrupted manner from the active area into the sense area. A first region from which source dopants and contacts have been excluded surrounds a periphery of the sense area. An etched region is disposed over the first region, thereby separating and electrically isolating the sense area metal layer from the active area metal layer.Type: GrantFiled: December 10, 2002Date of Patent: June 14, 2005Assignee: Fairchild Semiconductor CorporationInventors: Joseph A. Yedinak, Dwayne S. Reichl, Douglas J. Lange
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Patent number: 6798019Abstract: An IGBT has striped cell with source stripes 2a, 2b continuous or segmented along the length of the base stripe 3. The opposite stripes are periodically connected together by the N+ contact regions 20 to provide channel resistance along the width of the source stripes 2a, 2b. For continuous stripes the resistance between two sequential contact areas 20a, 20b is greatest in the middle and current concentrates near the source contact regions 20. The wider the spacing between the contacts 20, the larger the resistive drop to the midpoint between two N+ contacts 20.Type: GrantFiled: January 23, 2002Date of Patent: September 28, 2004Assignee: Fairchild Semiconductor CorporationInventors: Joseph A. Yedinak, Dwayne S. Reichl, Jack E. Wojslawowicz, Bernard J. Czeck, Robert D. Baran, Douglas Lange
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Publication number: 20040135213Abstract: An integrated circuit includes a die having a device layer. An insulating layer is disposed over the device layer. A die street defines the outermost bounds of the die. A voltage divider network including a plurality of resistive elements derives a plurality of predetermined bias voltages. A field plate termination includes a plurality of field plates disposed on the oxide layer and are laterally spaced apart relative to each other and relative to the die street. Each of the plurality of field plates is electrically connected to a corresponding bias voltage. The bias voltage applied to a given field plate is determined by and increases with the proximity of that field plate relative to the die street.Type: ApplicationFiled: October 9, 2003Publication date: July 15, 2004Inventors: Joseph A. Yedinak, Dwayne S. Reichl, Bernard J. Czeck, Douglas J. Lange
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Publication number: 20030141522Abstract: An integrated circuit die includes an active area having source dopants and contacts. An active area metal layer overlies the active area. A sense area is disposed on the die. A sense area metal layer overlies the sense area. A plurality of polysilicon gate stripes, polysilicon openings, and body stripes are disposed on the die, and extend in a continuous and uninterrupted manner from the active area into the sense area. A first region from which source dopants and contacts have been excluded surrounds a periphery of the sense area. An etched region is disposed over the first region, thereby separating and electrically isolating the sense area metal layer from the active area metal layer.Type: ApplicationFiled: December 10, 2002Publication date: July 31, 2003Inventors: Joseph A. Yedinak, Dwayne S. Reichl, Douglas J. Lange
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Publication number: 20030137015Abstract: An IGBT has striped cell with source stripes 2a, 2b continuous or segmented along the length of the base stripe 3. The opposite stripes are periodically connected together by the N+ contact regions 20 to provide channel resistance along the width of the source stripes 2a, 2b. For continuous stripes the resistance between two sequential contact areas 20a, 20b is greatest in the middle and current concentrates near the source contact regions 20. The wider the spacing between the contacts 20, the larger the resistive drop to the midpoint between two N+ contacts 20.Type: ApplicationFiled: January 23, 2002Publication date: July 24, 2003Inventors: Joseph A. Yedinak, Dwayne S. Reichl, Jack E. Wojslawowicz, Bernard J. Czeck, Robert D. Baran, Douglas Lange