Abstract: Described is a personal computer system that includes a first housing coupled to a second housing with a multi-conductor cable. The first housing includes an IDE direct access storage device having an opening for receiving a removable storage medium. The second housing is separate from the first housing and includes a microprocessor coupled to a local bus and an expansion bus, a first IDE controller, a non-volatile storage device coupled to the local bus and a power supply. The cable is coupled to the first and second housings for electrically connecting devices in the first housing to devices in the second housing. The second housing has a first interface coupled to the expansion bus, the first IDE controller and the cable. The first housing includes a second interface coupled to the cable and the IDE device.

Abstract: Disclosed is a split computer system that includes a first housing coupled to a second housing with a multi-conductor cable. The first housing includes a first direct access storage device (DASD) having an opening for receiving a removable storage medium. The second housing is separate from the first housing and includes a central processing unit (CPU) coupled to a local bus and an expansion bus, a non-volatile storage device coupled to the local bus, a second DASD coupled to the local bus and a power supply. The system further includes first and second DASD controllers coupled to the first and second DASDs respectively. The cable has one end coupled to the first housing and another end coupled to the second housing for electrically connecting devices in the first housing to devices in the second housing. The second housing has a first interface coupled to the expansion bus and the cable. The first housing also includes a second interface coupled to the cable and the first DASD.

Abstract: Advantage is taken of Very Large Scale Integrated (VLSI) circuit design and manufacture to provide, in a digital data handling system handling display signal streams, a video processor which is capable of high performance due to vector processing and special addressing modes. The video processor has, on a single VLSI device, a plurality of processors which cooperate for generating video signal streams and which employ distinctive addressing modes for memory elements of the device. Each of the plurality of processors has associated instruction and data caches, which are joined together by a wide data bus formed on the same substrate as the processors, and further has registers for controlling access, and the modes of access, to data held in memory.

Abstract: A digital data handling system handling display signal streams has a video processor which is capable of high performance due to vector processing and special addressing modes. The video processor is a single VLSI device having a plurality of processors, each of which has associated instruction and data caches, which are joined together by a wide data bus formed on the same substrate as the processors. Most audio and/or video compression algorithms use a Huffman style bit compression scheme with compression codes in variable length bit fields. The compressed data is a compacted bit stream which must be interpreted serially in order to extract the codes. In contrast to most microprocessors which process bit streams only inefficiently, the present invention uses a serialization FIFO to provide a hardware assist to the Huffman encoding/decoding.

Abstract: Advantage is taken of Very Large Scale Integrated (VLSI) circuit design and manufacture to provide, in a digital data handling system handling display signal streams, a video processor which is capable of high performance due to vector processing and special addressing modes. A single VLSI device has a plurality of processors which cooperate for generating video signal streams and which employ distinctive addressing modes for memory elements of the device. Each of the plurality of processors has associated instruction and data caches, and the processors are joined together by a wide data bus formed on the same substrate as the processors. Each processor has a load/store unit, a translation unit associated with the load/store unit, and an index control register for controlling any translation of data bit streams passed through the load/store unit.

Abstract: A digital data handling system handling display signal streams has a video processor which is capable of high performance due to vector processing and special addressing modes. The video processor is a single VLSI device having a plurality of processors, each of which has associated instruction and data caches, which are joined together by a wide data bus formed on the same substrate as the processors.

Abstract: A digital data handling system handling display signal streams has a video processor which is capable of high performance due to vector processing and special addressing modes. The video processor is a single VLSI device having a plurality of processors, each of which has associated instruction and data caches, which are joined together by a wide data bus formed on the same substrate as the processors. Any graphics subsystem must be able to support a variety of video formats, causing video refresh logic to become complicated. Such potential complications are avoided by the provision of a simple, general purpose hardware refresh system based on the direct color graphics frame buffer, with the broader range of services being provided by emulation using one of the processors included in the device.

Abstract: A computer system having four states of power management: a normal operating state, a standby state, a suspend state, and an off state. A control unit controls transitions between the various states. The standby state is characterized by devices, such as a video controller and a hard drive, being placed into a low-power mode transparent to the operating system and the applications executing on the computer system. The suspend state is characterized by executing code being interrupted and the state of the computer system being saved to a file on the hard drive in such a manner that system power may be removed after the state of the computer system is saved to the hard drive. Later, after system power is restored, the state of the computer system is resumed by reading from the hard drive and loading it in such a manner that the operating system and application programs are not adversely affected.

Abstract: A computer system having a CPU, a non-volatile storage device, a power management processor having a volatile power management configuration, and a power supply in circuit communication. Responsive to the AC power to the power supply being interrupted, the CPU restores the volatile power management configuration to said power management processor. The power management configuration comprises a value corresponding to a wake alarm and whether the power management processor responds to external events.

Abstract: A computer system having a CPU, a switch, a power supply, and power supply control logic for controlling the state of the power supply via a control signal. The power supply control logic comprises circuitry to interface control of the power supply between the CPU and the user via the switch. The power supply control logic further comprises a fault circuit that detects a fault condition in the power supply and negates the control signal, thereby clearing the fault condition in the power supply.

Abstract: A method of saving and restoring the state of a CPU operating code in protected mode on a computer system. The save method makes use of BIOS operating in shadow RAM located in a region where linear addresses equal physical addresses while saving the state of the CPU. The registers that cannot be directly saved to memory are determined by searching the system memory for data structures that correspond to the particular register. The restore method uses dummy page tables that point to the shadowed BIOS to allow the CPU to reenter protected mode without generating a protection fault.

Abstract: A suspend/resume computer system having a CPU, a non-volatile storage device, volatile registers and memory data, a power management processor, a backup suspend timer and a power supply in circuit communication. The power management processor controls the regulation of power to the CPU by the power supply. The suspend/resume system is controlled by an operating system having power management control. The backup suspend timer executes independently of the power management portion of the operating system. The backup suspend timer causes the system to suspend if the power management portion of the operating system ceases functioning and the system should otherwise be suspended.

Abstract: Advantage is taken of Very Large Scale Integrated (VLSI) circuit design and manufacture to provide, in a digital data handling system handling display signal streams, a video processor which is capable of high performance due to vector processing and asynchronous interrupt service. The VLSI device has a plurality of processors which cooperate for generating video signal streams and at least one and preferably at least two interrupt registers for controlling the operations of instruction data stream execution and interruption.

Abstract: A computer system having at least three states of power management: a normal operating state, a standby state, and a suspend state. The standby state is characterized by devices, such as a video controller and a hard drive, being placed into a low-power mode transparent to the operating system and the applications executing on the computer system. The suspend state is characterized by executing code being interrupted and the state of the computer system being saved to a file on the hard drive in such a manner that system power may be removed after the state of the computer system is saved to the hard drive. Later, after system power is restored, the state of the computer system is resumed by reading from the hard drive and loading it in such a manner that the operating system and application programs are not adversely affected.

Abstract: A computer system having four states of power management: a normal operating state, a standby state, a suspend state, and an off state. The standby state is characterized by devices, such as a video controller and a hard drive, being placed into a low-power mode transparent to the operating system and the applications executing on the computer system. The suspend state is characterized by executing code being interrupted and the state of the computer system being saved to a file on the hard drive in such a manner that system power may be removed after the state of the computer system is saved to the hard drive. Later, after system power is restored, the state of the computer system is resumed by reading from the hard drive and loading it in such a manner that the operating system and application programs are not adversely affected. The normal operating state and the off state correspond to the typical on and off states of more conventional computer systems.

Abstract: A computer system having a CPU, a power management processor, a switch, a modem, a timer, an override circuit, a glitch circuit, and a power supply in circuit communication. The power supply has several power supply states, which are controlled by the power management processor responsive to the CPU, the switch, the modem, the timer, the glitch circuit, the override circuit, and the power management processor itself.

Abstract: A computer system having a suspend/resume capability in addition to the normal operating state and the off state. Closure events of single momentary pushbutton switch control changes between the normal operating state, the suspend state, and the off state, depending on the value of a flag. If the flag is set in a certain state, closure events of the switch cause the computer system to change back and forth between the normal operating state and the off state. If the flag is set in a different state, closure events of the switch cause the computer system to change back and forth between the normal operating state and the suspend state. The switch also controls the video subsystem of the computer system such that pressing the switch blanks the video display terminal giving the user instantaneous feedback of the switch press.

Abstract: A computer system having a CPU, a non-volatile storage device, a power management processor having a volatile power management configuration, and a power supply in circuit communication. The power management processor controls the regulation of power to the CPU by the power supply. Prior to causing the power supply to cease providing regulated power to the CPU, the power management processor interrupts the CPU via a system management interrupt. Responsive to being interrupted via the system management interrupt, the CPU performs tasks associated with the power supply imminently ceasing to provide regulated power to the CPU. Such tasks include writing data to non-volatile memory and refreshing an alarm value in the power management processor. The CPU can extend the period of time before the power management processor causes the power supply to cease providing regulated power to the CPU while the CPU performs the necessary tasks.

Abstract: A desktop computer system having the capability to suspend and resume the state of the computer system. The suspended system state is saved to the system hard file such that system power may be removed, effectively allowing a system suspend requiring no power from the power supply.

Abstract: A method of saving and restoring the state of a CPU operating code in protected mode on a computer system. The save method makes use of BIOS operating in shadow RAM located in a region where linear addresses equal physical addresses while saving the state of the CPU. The registers that cannot be directly saved to memory are determined by searching the system memory for data structures that correspond to the particular register. The restore method uses dummy page tables that point to the shadowed BIOS to allow the CPU to reenter protected mode without generating a protection fault.