Abstract: Reduction in the base to collector capacitance of a heterojunction bipolar transistor, and, improved high frequency performance is achieved using existing materials and processes by undercutting the collector (5) under the base (7) along two parallel sides of the base mesa (7—FIG. 4), and providing a sloped collector edge (5—FIG. 6) along the remaining two parallel sides of the base. The foregoing is accomplished by selective etching and with the four sides of the mesa regions oriented as a non-rectangular parallelogram (7, 9—FIG. 4) in which one pair of sides is in parallel with one of the said [0 0 1] and [0 0 {overscore (1)}] planes of the crystalline structure and the other pair of sides in parallel with one of the [0 1 1] and [0 {overscore (1)} {overscore (1)}] planes of the crystalline structure.

Abstract: The invention relates to an integrated circuit structure that includes a substrate wafer having an active device layer disposed on a surface of the substrate wafer and having an electrically conductive element contained therein. The integrated circuit structure further comprises a barrier disposed between the substrate wafer and the active device layer, where the barrier blocks carriers injected into the substrate wafer and reduces low frequency oscillation effect.

Abstract: A method of selective molecular beam epitaxy for fabricating monolithically integrated circuit devices on a common substrate including combinations of PIN diode devices, HBT devices, HEMT devices and MESFET devices. The method includes depositing a profile layer of one of the devices on an appropriate substrate and then depositing a first dielectric layer over the profile layer. The profile layer and the dielectric layer are then etched to define a first device profile. A second profile layer for defining a second device is then deposited over the exposed substrate. The second profile is then selectively etched to define a second device profile. This process can be extended to more than two different device types monolithically integrated on a common substrate as long as the first developed devices are robust enough to handle the temperature cycling involved with developing the subsequent devices.

Abstract: The performance of a heterojunction bipolar transistor (HBT) operating at high power is limited by the power that can be dissipated by the device. This, in turn, is limited by the thermal resistance of the device to heat dissipation. In a typical HBT, and especially InP-based HBTs, heat generated during operation is concentrated near the collector-base junction. In order to more efficiently dissipate heat downward through the device to the substrate, both the collector and the sub-collector are formed of InP, which has a substantially lower thermal resistance than other typically used semiconductor materials.

Abstract: Reduction in the base to collector capacitance of a heterojunction bipolar transistor, and, improved high frequency performance is achieved using existing materials and processes by undercutting the collector (5) under the base (7) along two parallel sides of the base mesa (7—FIG. 4), and providing a sloped collector edge (5—FIG. 6) along the remaining two parallel sides of the base. The foregoing is accomplished by selective etching and with the four sides of the mesa regions oriented as a non-rectangular parallelogram (7, 9—FIG. 4) in which one pair of sides is in parallel with one of the said [0 0 1] and [0 0 {overscore (1)}] planes of the crystalline structure and the other pair of sides in parallel with one of the [0 1 1] and [0 {overscore (1)} {overscore (1)}] planes of the crystalline structure.

Abstract: A Schottky barrier diode and a method for fabricating a Schottky barrier diode that utilizes HBT active device layers. The Schottky barrier diode is formed with a vertically integrated profile on a GaAs substrate, with a subcollector layer and a collector layer. A suitable dielectric material is deposited on top of the collector layer. Vias are formed in the collector layer and subcollector layer for the barrier and ohmic contacts. The collector via is relatively deeply etched into the collector layer to lower the series resistance between the barrier and ohmic contacts, which results in relatively higher cut-off frequency performance.

Abstract: A Schottky barrier diode and a method for fabricating a Schottky barrier diode that utilizes HBT active device layers. The Schottky barrier diode is formed with a vertically integrated profile on a GaAs substrate, with a subcollector layer and a collector layer. A suitable dielectric material is deposited on top of the collector layer. Vias are formed in the collector layer and subcollector layer for the barrier and ohmic contacts. The collector via is relatively deeply etched into the collector layer to lower the series resistance between the barrier and ohmic contacts, which results in relatively higher cut-off frequency performance.

Abstract: A heterojunction bipolar transistor and a method for fabricating an HBT with self-aligned base metal contacts using a double photoresist, which requires fewer process steps than known methods, while minimizing damage to the active emitter contact region. In particular, a photoresist is used to form the emitter mesa. The emitter mesa photoresist is left on and a double polymethylmethacrylate (PMMA) and photoresist layer is then applied. The triple photoresist combination is patterned to create a non-critical lateral alignment for the base metal contacts to the emitter mesa, which permits selective base ohmic metal deposition and lift-off. By utilizing the double photoresist as opposed to a metal or dielectric for masking, an additional photolithography step and etching step is eliminated. By eliminating the need for an additional etching step, active regions of the semiconductors are prevented from being exposed to the etching step and possibly damaged.

Abstract: A heterojunction bipolar transistor with a vertically integrated profile includes a substrate layer, a collector contact layer, a collector layer, a base layer and an emitter layer, formed from AlGaAs, etched to form an emitter mesa leaving a relatively thin passivating layer, adjacent the emitter mesa. The base metal contacts are formed on the passivating layer, resulting in a wider bandgap, thus minimizing surface recombination velocity at the emitter-base junction and increasing the overall gain (.beta.) of the device. The base metal contacts are formed by evaporating a p-ohmic metal onto the n-type passivation layer. The p-ohmic contacts are annealed, resulting in p-type metal diffusion through the passivating layer and reaction with the base layer, resulting in ohmic contacts.

Abstract: A heterejunction bipolar transistor and a method for fabricating an HBT with self-aligned base metal contacts using a double photoresist, which requires fewer process steps than known methods, while minimizing damage to the active emitter contact region. In particular, a photoresist is used to form the emitter mesa. The emitter mesa photoresist is left on and a double polymethylmethacrylate (PMMA) and photoresist layer is then applied. The triple photoresist combination is patterned to create a non-critical lateral alignment for the base metal contacts to the emitter mesa, which permits selective base ohmic metal deposition and lift-off. By utilizing the double photoresist as opposed to a metal or dielectric for masking, an additional photolithography step and etching step is eliminated. By eliminating the need for an additional etching step, active regions of the semiconductors are prevented from being exposed to the etching step and possibly damaged.

Abstract: A pseudomorphic HEMT having a partially relaxed InGaAs channel layer. In order to increase device performance and lower the electron transport energy levels within the potential well defined by the conduction band of the channel layer, the channel layer thickness is increased beyond a critical thickness that defines where a strained InGaAs channel becomes relaxed and forms crystal lattice dislocations. The channel layer is partially relaxed in that the channel layer thickness exceeds the critical thickness, but the thickness of the channel layer is limited so that dislocations only form in a single direction.

Abstract: An InAlAs/InGaAlAs heterojunction bipolar transistor that includes a constant quaternary InGaAlAs collector layer. Graded InGaAlAs collector layers are provided on each side of the quaternary collector layer to minimize transitions through the constant collector layer. The InAlAs/InGaAlAs HBT may also include one or more of a graded InGaAlAs emitter-base transition region, a graded-doping InGaAs base layer, and a graded-composition InGaAlAs base layer.

Abstract: A thin film resistor with an insulating layer disposed between a substrate material and a resistor material is disclosed. Also, disclosed is a technique for fabricating this thin film resistor. In accordance with the preferred embodiment, the thin film resistor employs an insulating layer of silicon nitride with a thickness of 2000 .ANG.. The insulating layer prevents the resistor layer from diffusing into the substrate material which, in turn, significantly reduces variations in the resistor value during accelerated life testing. Compared to thin film resistors with a resistor layer evaporated directly upon a substrate material, reliability is increased from a few hundred hours up to thousands of hours. Also, the maximum current handling capability is increased by greater than one order of magnitude, which results in a thin film resistor which requires less surface area of a wafer.

Abstract: A high power pseudomorphic (PM) AlGaAs/InGaAs high electron mobility transistor (HEMT) (26) with improved gain at 94 GHz. The transistor (26) includes an InGaAs quantum well (32) having a silicon planar doping layer (34) located at the bottom. A donor layer (36) comprises AlGaAs with a silicon planar doping layer (37). The resulting transistor (26) exhibits superior gain and noise characteristics that relatively high power levels when operating at 94 GHz. The transistor (26) is produced using an optimized growth process which involves growing the quantum well at a relatively low temperature and then raising the temperature to grow subsequent layers.

Abstract: Disclosed is a method for fabricating complementary heterojunction bipolar transistors on a common substrate. The method comprises the steps of depositing a PNP profile by molecular beam epitaxy on an appropriate substrate and then depositing a layer of silicon nitride on the PNP profile just deposited. The substrate is then heated in a vacuum in order to densify the silicon nitride. A mask and resist layer are used to produce the desired PNP profile patterns. The NPN profile is deposited on the area of the substrate etched away as well as on the silicon nitride layer protecting the already deposited PNP layers. The NPN profile is then patterned using a resist and masking process. The polycrystalline NPN area on top of the silicon nitride layer and the remaining silicon nitride layer are etched away forming two adjacent complementary NPN and PNP profiles on a common substrate.

Abstract: This invention discloses a multiple quantum well infrared detector comprising a series of alternating layers of blocking layers and composite well layers. Each composite well layer is comprised of alternating layers of GaAs and AlGaAs forming a tightly coupled well group. The tightly coupled well group allows more allowed states for an electron released from the valence bands of the gallium arsenide semiconductor material. Consequently, there is a wider band width of detectable infrared radiation by the composite wall structure over the single well of the prior art.

Abstract: A technique for producing high reliability GaAsAlGaAs heterojunction bipolar transistors by Molecular Beam Epitaxy with beryllium base doping. Beryllium incorporation and diffusion, during base-layer deposition, is controlled through a combination of reduced substrate temperature and increase As/Ga flux ratio during MBE growth resulting in extremely stable heterojunction bipolar transistor profiles. In addition, graded InGaAs surface layers with non-alloyed refractory metal contacts are shown to significantly improve ohmic reliability to alloyed AuGe contacts. High gain (DC beta) is achieved by the use of an increased substrate temperature during emitter deposition. The HBTs in accordance with the present invention are useful in a number of important microwave applications such as log amps, a/d converters, and sample and hold circuits where high reliability is desired.

Abstract: A method for achieving extreme and arbitrary doping profiles in semiconductors with dopant concentrations varying over orders of magnitude in a few atomic layers. The method involves evaporating the semiconductor, along with the desired amounts of n- or p- dopants onto an atomically clean substrate semiconductor surface in an ultrahigh vacuum environment at low temperatures such that an amorphous film results. The amorphous film is then crystallized epitaxially by a solid phase epitaxy, thereby providing a single crystal with the desired dopant profile. Multiple profile changes or grading may be included in the semiconductor film by varying dopant concentrations in the amorphous layer as desired.