Patents by Inventor Dwight D. Diercks

Dwight D. Diercks has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and system for coordinated data execution using a primary graphics processor and a secondary graphics processor
    Patent number: 9471952
    Abstract: A method and system for coordinated data execution in a computer system. The system includes a first graphics processor coupled to a first memory and a second graphics processor coupled to a second memory. A graphics bus is configured to couple the first graphics processor and the second graphics processor. The first graphics processor and the second graphics processor are configured for coordinated data execution via communication across the graphics bus.
    Type: Grant
    Filed: February 5, 2013
    Date of Patent: October 18, 2016
    Assignee: NVIDIA CORPORATION
    Inventors: Dwight D. Diercks, Abraham B. De Waal
  • Method and system for coordinated data execution using a primary graphics processor and a secondary graphics processor
    Patent number: 8749561
    Abstract: A method and system for coordinated data execution in a computer system. The system includes a first graphics processor coupled to a first memory and a second graphics processor coupled to a second memory. A graphics bus is configured to couple the first graphics processor and the second graphics processor. The first graphics processor and the second graphics processor are configured for coordinated data execution via communication across the graphics bus.
    Type: Grant
    Filed: March 14, 2003
    Date of Patent: June 10, 2014
    Assignee: NVIDIA Corporation
    Inventors: Dwight D. Diercks, Abraham B. de Waal
  • METHOD AND SYSTEM FOR COORDINATED DATA EXECUTION USING A PRIMARY GRAPHICS PROCESSOR AND A SECONDARY GRAPHICS PROCESSOR
    Publication number: 20140055465
    Abstract: A method and system for coordinated data execution in a computer system. The system includes a first graphics processor coupled to a first memory and a second graphics processor coupled to a second memory. A graphics bus is configured to couple the first graphics processor and the second graphics processor. The first graphics processor and the second graphics processor are configured for coordinated data execution via communication across the graphics bus.
    Type: Application
    Filed: February 5, 2013
    Publication date: February 27, 2014
    Applicant: NVIDIA CORPORATION
    Inventors: Dwight D. Diercks, Abraham B. De Waal