Abstract: A print head assembly for a media processing device comprises: a print head including an interface and a latch receiver on an upper surface of the print head; and a print head carrier including: (i) a base plate having an opening to receive the latch receiver therethrough when the print head is positioned at a lower surface of the base plate; (ii) an adapter to engage with the interface of the print head; and (iii) a latch bar on an upper surface of the base plate, the latch bar slideable between a first position to engage with the latch receiver and lock the print head to the base plate, and a second position to disengage from the latch receiver and release the print head from the base plate.

Abstract: A print head assembly for a media processing device comprises: a print head including an interface and a latch receiver on an upper surface of the print head; and a print head carrier including: (i) a base plate having an opening to receive the latch receiver therethrough when the print head is positioned at a lower surface of the base plate; (ii) an adapter to engage with the interface of the print head; and (iii) a latch bar on an upper surface of the base plate, the latch bar slideable between a first position to engage with the latch receiver and lock the print head to the base plate, and a second position to disengage from the latch receiver and release the print head from the base plate.

Abstract: A media processing device is disclosed. An example media processing device includes memory including machine-readable instructions; and a processor to execute the machine-readable instructions to control a printhead assembly, the processor being configured to communicate with the printhead assembly in accordance with a pin configuration, wherein the pin configuration includes pin groups, and each of the pin groups includes a signal line and a reference voltage, wherein the signal line pin is coupled to a source of changing values, and the reference voltage pin is coupled to a constant voltage.

Abstract: A media processing device is disclosed. An example media processing device includes memory including machine-readable instructions; and a processor to execute the machine-readable instructions to control a printhead assembly, the processor being configured to communicate with the printhead assembly in accordance with a pin configuration, wherein the pin configuration includes pin groups, and each of the pin groups includes a signal line and a reference voltage, wherein the signal line pin is coupled to a source of changing values, and the reference voltage pin is coupled to a constant voltage.

Abstract: Printhead pin configurations are disclosed. An example printhead assembly includes an interface to place the printhead assembly in communication with a logic circuit; and a logic circuit configured according to a pin configuration, the pin configuration comprising pin groups, wherein each of the pin groups includes a signal line and a reference voltage.

Abstract: Printhead pin configurations are disclosed. An example printhead assembly includes an interface to place the printhead assembly in communication with a logic circuit; and a logic circuit configured according to a pin configuration, the pin configuration comprising pin groups, wherein each of the pin groups includes a signal line and a reference voltage.

Abstract: Systems, methods, and apparatuses are disclosed for providing a high speed adaptive thermal printhead interface. In one embodiment, an apparatus is provided comprising at least one processor; and at least one memory including computer program instructions, the computer program instructions being configured to, when executed by the at least one processor, cause the apparatus at least to determine identifier information for a connected printhead; retrieve printhead interface configuration data for a configurable printhead interface based at least in part on the identifier information; configure printhead interface circuitry in accordance with the printhead interface configuration data; and enable communication with the printhead through the configurable printhead interface.

Abstract: Systems, methods, and apparatuses are disclosed for providing a high speed adaptive thermal printhead interface. In one embodiment, an apparatus is provided comprising at least one processor; and at least one memory including computer program instructions, the computer program instructions being configured to, when executed by the at least one processor, cause the apparatus at least to determine identifier information for a connected printhead; retrieve printhead interface configuration data for a configurable printhead interface based at least in part on the identifier information; configure printhead interface circuitry in accordance with the printhead interface configuration data; and enable communication with the printhead through the configurable printhead interface.

Abstract: A method and apparatus for detecting the presence and the type of network devices connected to a management device via transmission lines. The apparatus may include a pull-up resistor, a pull-down resistor, a filter, and a presence detector, the resistors superimposing a DC or low-frequency voltage on the transmission line. The impact, if any, of the DC voltage one communications equipment and circuitry can be reduced by a coupling that isolates the DC voltage. Similarly, the filter prevents transmitted data signals from interfering with the DC voltage level. The method and apparatus function regardless of whether the network device is functional or powered on, and different values of pull-up or pull-down resistors can be used to indicate the type of device that terminates the transmission line.

Abstract: A multi-service access platform may have network interface cards and application cards. The network interface cards may interface the multi-service access platform to an ingress network and an egress network. The network interface cards may be coupled to the application cards by a network distribution bus. As a result, the application cards may perform digital signal processing on signals received from the ingress network. Additionally, the application cards may be coupled to a packet switching fabric. The packet switching fabric may facilitate exchange of signals between the application cards. Additionally, the packet switching fabric may permit exchange of the signals with the egress network.

Abstract: A method and apparatus for detecting the presence and the type of network devices connected to a management device via transmission lines. The apparatus may include a pull-up resistor, a pull-down resistor, a filter, and a presence detector, the resistors superimposing a DC or low-frequency voltage on the transmission line. The impact, if any, of the DC voltage one communications equipment and circuitry can be reduced by a coupling that isolates the DC voltage. Similarly, the filter prevents transmitted data signals from interfering with the DC voltage level. The method and apparatus function regardless of whether the network device is functional or powered on, and different values of pull-up or pull-down resistors can be used to indicate the type of device that terminates the transmission line.

Abstract: An image processor having an image algorithm processor (66) operating under control of a writable control store (94), and a number of parallel image processors (72) operating under control of instruction words from a writable control store (100). An image memory controller (68) receives memory addresses from the image algorithm processor (66) for coordinating the reading and writing of an image memory (82) using pixel data processed by the parallel image processor set (72). The image memory controller (68) arbitrates memory address request cycles, memory refresh cycles and screen refresh cycles. The image memory (82) includes different planes (84, 86 and 88) associated with red, green and blue pixel data. Associated with each image memory plane is a video processor (106) for converting parallel image data to high speed serial image data.

Abstract: An image processor having an image algorithm processor (66) operating under control of a writable control store (94), and a number of parallel image processors (72) operating under control of instruction words from a writable control store (100). An image memory controller (68) receives memory addresses from the image algorithm processor (66) for coordinating the reading and writing of an image memory (82) using pixel data processed by the parallel image processor set (72). The image memory controller (68) arbitrates memory address request cycles, memory refresh cycles and screen refresh cycles. The image memory (82) includes different planes (84, 86 and 88) assocated with red, green and blue pixel data. Associated with each image memory plane is a video processor (106) for converting parallel image data to high speed serial image data.

Abstract: Disclosed is an image processor having an image algorithm processor (66) operating under control of a writable control store (94), and a number of parallel image processors (72) operating under control of instruction words from a writable control store (100). An image memory controller (68) receives memory addresses from the image algorithm processor (66) for coordinating the reading and writing of an image memory (82) using pixel data processed by the parallel image processor set (72). The image memory controller (68) arbitrates memory address request cycles, memory refresh cycles and screen refresh cycles. The image memory (82) includes different planes (84, 86 and 88) associated with red, green and blue pixel data. Associated with each image memory plane is a video processor (106) for converting parallel image data to high speed serial image data.

Abstract: An image processor having an image algorithm processor (66) operating under control of a writable control store (94), and a number of parallel image processors (72) operating under control of instruction words from a writable control store (100). An image memory controller (68) receives memory addresses from the image algorithm processor (66) for coordinating the reading and writing of an image memory (82) using pixel data processed by the parallel image processor set (72). The image memory controller (68) arbitrates memory address request cycles, memory refresh cycles and screen refresh cycles. The image memory (82) includes different planes (84, 86 and 88) associated with red, green and blue pixel data. Associated with each image memory plane is a video processor (106) for converting parallel image data to high speed serial image data.

Abstract: Disclosed is an image processor having an image algorithm processor (66) operating under control of a writable control store (94), and a number of parallel image processors (72) operating under control of instruction words from a writable control store (100). An image memory controller (68) receives memory addresses from the image algorithm processor (66) for coordinating the reading and writing of an image memory (82) using pixel data processed by the parallel image processor set (72). The image memory controller (68) arbitrates memory address request cycles, memory refresh cycles and screen refresh cycles. The image memory (82) includes different planes (84, 86 and 88) associated with red, green and blue pixel data. Associated with each image memory plane is a video processor (106) for converting parallel image data to high speed serial image data.