Patents by Inventor Dwight D. Riley

Dwight D. Riley has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230421451
    Abstract: An apparatus in a first computing device is provided. During operation, the apparatus can present, to a processor of the first computing device, a virtual interface switch (VIS) coupled to an interface port of the processor. The apparatus can present to the processor that a target device, which is reachable via a remote apparatus of a second computing device, is coupled to the VIS. The apparatuses can be coupled via at least a first fabric and a second fabric. A respective fabric may facilitate communication based on a fabric switching protocol. The apparatus can obtain a set of packets, which can be issued from the interface port via the VIS and directed to the target device. The apparatus can then forward, to the remote apparatus, a first subset of the set of packets via the first fabric and a second subset of the set of packets via the second fabric.
    Type: Application
    Filed: September 11, 2023
    Publication date: December 28, 2023
    Inventors: Montgomery C. McGraw, Dwight D. Riley
  • Publication number: 20230353477
    Abstract: A process includes enforcing compliance of a compute appliance to a reference operating state for the compute appliance. The compute appliance is part of a cloud-based computing system. Enforcing compliance with the reference operating state includes, responsive to a startup of the compute appliance, the compute appliance determining an actual compute state of the compute appliance. The actual compute state includes an actual physical topology placement of a hardware component of the compute appliance. Determining the actual compute state includes determining the physical topology placement of the hardware component. Enforcing compliance with the reference operating state includes verifying whether the actual compute state complies with the reference compute state. The verification includes comparing the actual compute state to the reference compute state.
    Type: Application
    Filed: April 28, 2022
    Publication date: November 2, 2023
    Inventors: Dwight D. Riley, Robert W. Noller
  • Patent number: 11765037
    Abstract: An apparatus in a first computing device is provided. During operation, the apparatus can present, to a processor of the first computing device, a virtual interface switch (VIS) coupled to an interface port of the processor. The apparatus can present to the processor that a target device, which is reachable via a remote apparatus of a second computing device, is coupled to the VIS. The apparatuses can be coupled via at least a first fabric and a second fabric. A respective fabric may facilitate communication based on a fabric switching protocol. The apparatus can obtain a set of packets, which can be issued from the interface port via the VIS and directed to the target device. The apparatus can then forward, to the remote apparatus, a first subset of the set of packets via the first fabric and a second subset of the set of packets via the second fabric.
    Type: Grant
    Filed: August 19, 2020
    Date of Patent: September 19, 2023
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Montgomery C. McGraw, Dwight D. Riley
  • Publication number: 20230132853
    Abstract: A supervisory service of a node that includes a smart input/output (I/O) peripheral is extended into a cloud operator domain that is associated with the smart I/O peripheral. The supervisory service determines a state of a ready state indicator that is provided by the smart I/O peripheral. Based on the state, the supervisory service performs at least one of regulating an availability of an instance of an application operating environment of the node or determining whether the smart I/O peripheral is ready to be configured by the supervisory service.
    Type: Application
    Filed: October 29, 2021
    Publication date: May 4, 2023
    Inventors: Dwight D. Riley, Scott P. Faasse
  • Patent number: 11625338
    Abstract: A supervisory service of a node that includes a smart input/output (I/O) peripheral is extended into a cloud operator domain that is associated with the smart I/O peripheral. The supervisory service determines a state of a ready state indicator that is provided by the smart I/O peripheral. Based on the state, the supervisory service performs at least one of regulating an availability of an instance of an application operating environment of the node or determining whether the smart I/O peripheral is ready to be configured by the supervisory service.
    Type: Grant
    Filed: October 29, 2021
    Date of Patent: April 11, 2023
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Dwight D. Riley, Scott P. Faasse
  • Publication number: 20220350767
    Abstract: Composable computing architectures with an interconnection fabric to provide high availability and fault tolerance are described. An interconnection fabric routes packets between compute resources, memory resources, and input/output (I/O) resources. A fabric manager is coupled with the interconnection fabric to receive an I/O or memory requirement for a compute workload for a host device, and to map individual I/O or memory resources from the plurality of I/O resources to individual compute resources from the plurality of compute resource and to dynamically map individual I/O resources from the plurality of I/O resources based on received resource requests.
    Type: Application
    Filed: April 30, 2021
    Publication date: November 3, 2022
    Inventors: Montgomery C. McGraw, Dwight D. Riley
  • Publication number: 20220060382
    Abstract: An apparatus in a first computing device is provided. During operation, the apparatus can present, to a processor of the first computing device, a virtual interface switch (VIS) coupled to an interface port of the processor. The apparatus can present to the processor that a target device, which is reachable via a remote apparatus of a second computing device, is coupled to the VIS. The apparatuses can be coupled via at least a first fabric and a second fabric. A respective fabric may facilitate communication based on a fabric switching protocol. The apparatus can obtain a set of packets, which can be issued from the interface port via the VIS and directed to the target device. The apparatus can then forward, to the remote apparatus, a first subset of the set of packets via the first fabric and a second subset of the set of packets via the second fabric.
    Type: Application
    Filed: August 19, 2020
    Publication date: February 24, 2022
    Inventors: Montgomery C. McGraw, Dwight D. Riley
  • Patent number: 11226908
    Abstract: In exemplary aspects described herein, system memory is secured using protected memory regions. Portions of a system memory are assigned to endpoint devices, such as peripheral component interconnect express (PCIe) compliant devices. The portions of the system memory can include protected memory regions. The protected memory regions of the system memory assigned to each of the endpoint devices are configured to control access thereto using device identifiers and/or process identifiers, such as a process address space ID (PASID). When a transaction request is received by a device, the memory included in that request is used to determine whether it corresponds to a protected memory region. If so, the transaction request is executed if the identifiers in the request match the identifiers for which access is allowed to that protected memory region.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: January 18, 2022
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Dwight D. Riley, Shiva R. Dasari
  • Publication number: 20210034547
    Abstract: In exemplary aspects described herein, system memory is secured using protected memory regions. Portions of a system memory are assigned to endpoint devices, such as peripheral component interconnect express (PCIe) compliant devices. The portions of the system memory can include protected memory regions. The protected memory regions of the system memory assigned to each of the endpoint devices are configured to control access thereto using device identifiers and/or process identifiers, such as a process address space ID (PASID). When a transaction request is received by a device, the memory included in that request is used to determine whether it corresponds to a protected memory region. If so, the transaction request is executed if the identifiers in the request match the identifiers for which access is allowed to that protected memory region.
    Type: Application
    Filed: July 31, 2019
    Publication date: February 4, 2021
    Inventors: Dwight D. Riley, Shiva R. Dasari
  • Patent number: 10649680
    Abstract: According to an example, a dual-port non-volatile dual in-line memory module (NVDIMM) includes a first port to provide a central processing unit (CPU) with access to universal memory of the dual-port NVDIMM and a second port to provide an external NVDIMM manager circuit with access to the universal memory of the dual-port NVDIMM. Accordingly, a media controller of the dual-port NVDIMM may store data received from the CPU through the first port in the universal memory, control dual-port settings received from the CPU, and transmit the stored data to the NVDIMM manager circuit through the second port of the dual-port NVDIMM.
    Type: Grant
    Filed: April 30, 2015
    Date of Patent: May 12, 2020
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Dwight D. Riley, Joseph E. Foster, Thierry Fevrier
  • Publication number: 20190069436
    Abstract: Example implementations relate to a locking mechanism of a module of a data center. In some examples, a controller may comprise a processing resource and a memory resource storing machine-readable instructions to receive a request to unlock a locking mechanism of a module of a data center, authenticate a user associated with the request to unlock the locking mechanism by comparing credentials included with the unlock request with permissions associated with the user, and unlock the locking mechanism of the module of the data center in response to the credentials having proper permissions.
    Type: Application
    Filed: August 23, 2017
    Publication date: February 28, 2019
    Inventors: John Norton, Dwight D. Riley
  • Patent number: 10157017
    Abstract: According to an example, data may be replicated using a dual-port nonvolatile dual in-line memory module (NVDIMM). A processor may request, through a first port of the dual-port NVDIMM, to store data to universal memory of the dual-port NVDIMM and to commit the data to remote storage according to a high-availability storage capability of the dual-port NVDIMM. The process may then receive a notification from the dual-port NVDIMM that the data has been transparently committed to the remote storage through a second port of the dual-port NVDIMM.
    Type: Grant
    Filed: April 30, 2015
    Date of Patent: December 18, 2018
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Dwight D. Riley, Joseph E. Foster, Thierry Fevrier
  • Publication number: 20180004422
    Abstract: According to an example, a dual-port non-volatile dual in-line memory module (NVDIMM) includes a first port to provide a central processing unit (CPU) with access to universal memory of the dual-port NVDIMM and a second port to provide an external NVDIMM manager circuit with access to the universal memory of the dual-port NVDIMM. Accordingly, a media controller of the dual-port NVDIMM may store data received from the CPU through the first port in the universal memory, control dual-port settings received from the CPU, and transmit the stored data to the NVDIMM manager circuit through the second port of the dual-port NVDIMM.
    Type: Application
    Filed: April 30, 2015
    Publication date: January 4, 2018
    Inventors: Dwight D. Riley, Joseph E. Foster, Thierry Fevrier
  • Publication number: 20170371776
    Abstract: According to an example, a fabric manager server may migrate data stored in a dual-interface non-volatile dual in-line memory module (NVDIMM) of a memory application server. The fabric manager server may receive data routing preferences for a memory fabric and retrieve the data stored in universal memory of the dual-port NVDIMM according to the data routing preferences through a second port of the dual-port NVDIMM. The retrieved data may then be routed from the dual-port NVDIMM for replication to remote storage according to the data routing preferences. Once the retrieved data is replicated to remote storage, the fabric manager may alert the dual-port NVDIMM.
    Type: Application
    Filed: April 30, 2015
    Publication date: December 28, 2017
    Inventors: Dwight D. Riley, Thierry Fevrier, Joseph E. Foster
  • Publication number: 20170242593
    Abstract: According to an example, data may be replicated using a dual-port nonvolatile dual in-line memory module (NVDIMM). A processor may request, through a first port of the dual-port NVDIMM, to store data to universal memory of the dual-port NVDIMM and to commit the data to remote storage according to a high-availability storage capability of the dual-port NVDIMM. The process may then receive a notification from the dual-port NVDIMM that the data has been transparently committed to the remote storage through a second port of the dual-port NVDIMM.
    Type: Application
    Filed: April 30, 2015
    Publication date: August 24, 2017
    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
    Inventors: Dwight D. RILEY, Joseph E. FOSTER, Thierry FEVRIER
  • Patent number: 9037768
    Abstract: Embodiments of the present invention are directed to methods for virtualizing interrupt modes on behalf of interrupt-generating devices, including I/O-device controllers, so that newer interrupt-generating devices that lack older interrupt modes can be used in systems that continue to rely on older interrupt modes. In one embodiment of the present invention, a PCIe switch or PCIe-based host bridge is modified, or a new component introduced, to provide an interrupt-mode virtualizing function, or virtual interrupt-mode interface, that provides a virtual interrupt mode on behalf of interrupt-generating devices, such as I/O-device controllers, to operating systems, BIOS layers, and other components that communicate with the I/O-device controllers.
    Type: Grant
    Filed: April 28, 2008
    Date of Patent: May 19, 2015
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Hubert E. Brinkmann, Paul V. Brownell, David L. Matthews, Dwight D. Riley
  • Patent number: 8782289
    Abstract: In one embodiment, a computer system, comprises at least one host node, at least one input/output node coupled to the host node, at least one multi-function device coupled to the input/output node via a switch, and a middle manager processor comprising logic to block an enumeration process in a host node for the multi-function devices behind the switch hierarchy, initiate an enumeration process for the multi-function devices in a manager processor separate from the host node, store a routing table for the switch hierarchy in a memory module coupled to the manager processor, and allocate, in the manager processor, endpoint device resources to the host node.
    Type: Grant
    Filed: June 10, 2008
    Date of Patent: July 15, 2014
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: David L. Matthews, Hubert E. Brinkmann, James Xuan Dinh, Dwight D. Riley, Paul V. Brownell
  • Patent number: 8464260
    Abstract: A hardware device interface supporting transaction authentication is described herein. At least some illustrative embodiments include a device, including an interconnect interface, and processing logic (coupled to the bus interface) that provides access to a plurality of functions of the device through the interconnect interface. A first transaction received by the device, and associated with a function of the plurality of functions, causes a request identifier within the first transaction to be assigned to the function. Access to the function is denied if a request identifier of a second transaction, subsequent to the first transaction, does not match the request identifier assigned to the function.
    Type: Grant
    Filed: October 31, 2007
    Date of Patent: June 11, 2013
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: Dwight D. Riley
  • Patent number: 8374175
    Abstract: A system and method for remote direct memory access over a network switch fabric. Some illustrative embodiments may include a system comprising a first system node, a direct memory access (DMA) controller, a second system node, and a network switch fabric coupling together the first and second system nodes (the network switch fabric comprises a rooted hierarchical bus). The DMA controller is configured to perform a DMA transfer of data between the first and second system nodes across the network switch fabric. The data is formatted as one or more remote DMA (RDMA) protocol messages that are routed across the network switch fabric based on a bus end-device identifier corresponding to the second system node.
    Type: Grant
    Filed: April 27, 2005
    Date of Patent: February 12, 2013
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: Dwight D. Riley
  • Patent number: 8316377
    Abstract: Systems and methods of sharing legacy devices in a multi-host environment are disclosed. An exemplary method for sharing legacy devices in a multi-host environment includes receiving device information from a legacy device, the device information identifying a target within a virtual machine. The method also includes encapsulating the device information into a corresponding bus transaction for a network switch fabric. The method also includes routing the bus transaction over the network switch fabric in the virtual machine to a host within the virtual machine.
    Type: Grant
    Filed: September 6, 2007
    Date of Patent: November 20, 2012
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: Dwight D. Riley