Abstract: Composable computing architectures with an interconnection fabric to provide high availability and fault tolerance are described. An interconnection fabric routes packets between compute resources, memory resources, and input/output (I/O) resources. A fabric manager is coupled with the interconnection fabric to receive an I/O or memory requirement for a compute workload for a host device, and to map individual I/O or memory resources from the plurality of I/O resources to individual compute resources from the plurality of compute resource and to dynamically map individual I/O resources from the plurality of I/O resources based on received resource requests.

Abstract: In some examples, a security chip for an electronic device includes a nonvolatile memory to store a collection of encryption keys for encrypting information to produce encrypted information. The security chip includes a discrete secure erase hardware logic and is separate from a collection of device processors of the electronic device. The discrete secure erase hardware logic receives an erase indication indicating a request to erase the encrypted information. In response to the erase indication, the discrete secure erase hardware logic erases the collection of encryption keys in the nonvolatile memory, and activates an output indication to cause activation of an erase indicator at the electronic device.

Abstract: A process includes enforcing compliance of a compute appliance to a reference operating state for the compute appliance. The compute appliance is part of a cloud-based computing system. Enforcing compliance with the reference operating state includes, responsive to a startup of the compute appliance, the compute appliance determining an actual compute state of the compute appliance. The actual compute state includes an actual physical topology placement of a hardware component of the compute appliance. Determining the actual compute state includes determining the physical topology placement of the hardware component. Enforcing compliance with the reference operating state includes verifying whether the actual compute state complies with the reference compute state. The verification includes comparing the actual compute state to the reference compute state.

Abstract: An apparatus in a first computing device is provided. During operation, the apparatus can present, to a processor of the first computing device, a virtual interface switch (VIS) coupled to an interface port of the processor. The apparatus can present to the processor that a target device, which is reachable via a remote apparatus of a second computing device, is coupled to the VIS. The apparatuses can be coupled via at least a first fabric and a second fabric. A respective fabric may facilitate communication based on a fabric switching protocol. The apparatus can obtain a set of packets, which can be issued from the interface port via the VIS and directed to the target device. The apparatus can then forward, to the remote apparatus, a first subset of the set of packets via the first fabric and a second subset of the set of packets via the second fabric.

Abstract: A process includes enforcing compliance of a compute appliance to a reference operating state for the compute appliance. The compute appliance is part of a cloud-based computing system. Enforcing compliance with the reference operating state includes, responsive to a startup of the compute appliance, the compute appliance determining an actual compute state of the compute appliance. The actual compute state includes an actual physical topology placement of a hardware component of the compute appliance. Determining the actual compute state includes determining the physical topology placement of the hardware component. Enforcing compliance with the reference operating state includes verifying whether the actual compute state complies with the reference compute state. The verification includes comparing the actual compute state to the reference compute state.

Abstract: An apparatus in a first computing device is provided. During operation, the apparatus can present, to a processor of the first computing device, a virtual interface switch (VIS) coupled to an interface port of the processor. The apparatus can present to the processor that a target device, which is reachable via a remote apparatus of a second computing device, is coupled to the VIS. The apparatuses can be coupled via at least a first fabric and a second fabric. A respective fabric may facilitate communication based on a fabric switching protocol. The apparatus can obtain a set of packets, which can be issued from the interface port via the VIS and directed to the target device. The apparatus can then forward, to the remote apparatus, a first subset of the set of packets via the first fabric and a second subset of the set of packets via the second fabric.

Abstract: A supervisory service of a node that includes a smart input/output (I/O) peripheral is extended into a cloud operator domain that is associated with the smart I/O peripheral. The supervisory service determines a state of a ready state indicator that is provided by the smart I/O peripheral. Based on the state, the supervisory service performs at least one of regulating an availability of an instance of an application operating environment of the node or determining whether the smart I/O peripheral is ready to be configured by the supervisory service.

Abstract: A supervisory service of a node that includes a smart input/output (I/O) peripheral is extended into a cloud operator domain that is associated with the smart I/O peripheral. The supervisory service determines a state of a ready state indicator that is provided by the smart I/O peripheral. Based on the state, the supervisory service performs at least one of regulating an availability of an instance of an application operating environment of the node or determining whether the smart I/O peripheral is ready to be configured by the supervisory service.

Abstract: Composable computing architectures with an interconnection fabric to provide high availability and fault tolerance are described. An interconnection fabric routes packets between compute resources, memory resources, and input/output (I/O) resources. A fabric manager is coupled with the interconnection fabric to receive an I/O or memory requirement for a compute workload for a host device, and to map individual I/O or memory resources from the plurality of I/O resources to individual compute resources from the plurality of compute resource and to dynamically map individual I/O resources from the plurality of I/O resources based on received resource requests.

Abstract: An apparatus in a first computing device is provided. During operation, the apparatus can present, to a processor of the first computing device, a virtual interface switch (VIS) coupled to an interface port of the processor. The apparatus can present to the processor that a target device, which is reachable via a remote apparatus of a second computing device, is coupled to the VIS. The apparatuses can be coupled via at least a first fabric and a second fabric. A respective fabric may facilitate communication based on a fabric switching protocol. The apparatus can obtain a set of packets, which can be issued from the interface port via the VIS and directed to the target device. The apparatus can then forward, to the remote apparatus, a first subset of the set of packets via the first fabric and a second subset of the set of packets via the second fabric.

Abstract: In exemplary aspects described herein, system memory is secured using protected memory regions. Portions of a system memory are assigned to endpoint devices, such as peripheral component interconnect express (PCIe) compliant devices. The portions of the system memory can include protected memory regions. The protected memory regions of the system memory assigned to each of the endpoint devices are configured to control access thereto using device identifiers and/or process identifiers, such as a process address space ID (PASID). When a transaction request is received by a device, the memory included in that request is used to determine whether it corresponds to a protected memory region. If so, the transaction request is executed if the identifiers in the request match the identifiers for which access is allowed to that protected memory region.

Abstract: In exemplary aspects described herein, system memory is secured using protected memory regions. Portions of a system memory are assigned to endpoint devices, such as peripheral component interconnect express (PCIe) compliant devices. The portions of the system memory can include protected memory regions. The protected memory regions of the system memory assigned to each of the endpoint devices are configured to control access thereto using device identifiers and/or process identifiers, such as a process address space ID (PASID). When a transaction request is received by a device, the memory included in that request is used to determine whether it corresponds to a protected memory region. If so, the transaction request is executed if the identifiers in the request match the identifiers for which access is allowed to that protected memory region.

Abstract: According to an example, a dual-port non-volatile dual in-line memory module (NVDIMM) includes a first port to provide a central processing unit (CPU) with access to universal memory of the dual-port NVDIMM and a second port to provide an external NVDIMM manager circuit with access to the universal memory of the dual-port NVDIMM. Accordingly, a media controller of the dual-port NVDIMM may store data received from the CPU through the first port in the universal memory, control dual-port settings received from the CPU, and transmit the stored data to the NVDIMM manager circuit through the second port of the dual-port NVDIMM.

Abstract: Example implementations relate to a locking mechanism of a module of a data center. In some examples, a controller may comprise a processing resource and a memory resource storing machine-readable instructions to receive a request to unlock a locking mechanism of a module of a data center, authenticate a user associated with the request to unlock the locking mechanism by comparing credentials included with the unlock request with permissions associated with the user, and unlock the locking mechanism of the module of the data center in response to the credentials having proper permissions.

Abstract: According to an example, data may be replicated using a dual-port nonvolatile dual in-line memory module (NVDIMM). A processor may request, through a first port of the dual-port NVDIMM, to store data to universal memory of the dual-port NVDIMM and to commit the data to remote storage according to a high-availability storage capability of the dual-port NVDIMM. The process may then receive a notification from the dual-port NVDIMM that the data has been transparently committed to the remote storage through a second port of the dual-port NVDIMM.

Abstract: According to an example, a dual-port non-volatile dual in-line memory module (NVDIMM) includes a first port to provide a central processing unit (CPU) with access to universal memory of the dual-port NVDIMM and a second port to provide an external NVDIMM manager circuit with access to the universal memory of the dual-port NVDIMM. Accordingly, a media controller of the dual-port NVDIMM may store data received from the CPU through the first port in the universal memory, control dual-port settings received from the CPU, and transmit the stored data to the NVDIMM manager circuit through the second port of the dual-port NVDIMM.

Abstract: According to an example, a fabric manager server may migrate data stored in a dual-interface non-volatile dual in-line memory module (NVDIMM) of a memory application server. The fabric manager server may receive data routing preferences for a memory fabric and retrieve the data stored in universal memory of the dual-port NVDIMM according to the data routing preferences through a second port of the dual-port NVDIMM. The retrieved data may then be routed from the dual-port NVDIMM for replication to remote storage according to the data routing preferences. Once the retrieved data is replicated to remote storage, the fabric manager may alert the dual-port NVDIMM.

Abstract: According to an example, data may be replicated using a dual-port nonvolatile dual in-line memory module (NVDIMM). A processor may request, through a first port of the dual-port NVDIMM, to store data to universal memory of the dual-port NVDIMM and to commit the data to remote storage according to a high-availability storage capability of the dual-port NVDIMM. The process may then receive a notification from the dual-port NVDIMM that the data has been transparently committed to the remote storage through a second port of the dual-port NVDIMM.

Abstract: Embodiments of the present invention are directed to methods for virtualizing interrupt modes on behalf of interrupt-generating devices, including I/O-device controllers, so that newer interrupt-generating devices that lack older interrupt modes can be used in systems that continue to rely on older interrupt modes. In one embodiment of the present invention, a PCIe switch or PCIe-based host bridge is modified, or a new component introduced, to provide an interrupt-mode virtualizing function, or virtual interrupt-mode interface, that provides a virtual interrupt mode on behalf of interrupt-generating devices, such as I/O-device controllers, to operating systems, BIOS layers, and other components that communicate with the I/O-device controllers.

Abstract: In one embodiment, a computer system, comprises at least one host node, at least one input/output node coupled to the host node, at least one multi-function device coupled to the input/output node via a switch, and a middle manager processor comprising logic to block an enumeration process in a host node for the multi-function devices behind the switch hierarchy, initiate an enumeration process for the multi-function devices in a manager processor separate from the host node, store a routing table for the switch hierarchy in a memory module coupled to the manager processor, and allocate, in the manager processor, endpoint device resources to the host node.