Patents by Inventor Dwight Manning

Dwight Manning has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and apparatus for avoiding dicing chip-outs in integrated circuit die
    Patent number: 7354790
    Abstract: A method and apparatus for avoiding dicing chip-outs in integrated circuit die comprises: (a) providing a wafer for forming a plurality of integrated circuit die thereon; (b) forming the plurality of integrated circuit die on the wafer; and (c) forming a saw street between the integrated circuit die on the wafer to relieve cutting stress in the wafer when the integrated circuit die are separated by a dicing saw.
    Type: Grant
    Filed: May 18, 2005
    Date of Patent: April 8, 2008
    Assignee: LSI Logic Corporation
    Inventors: Parthasarathy Rajagopalan, Zafer Kutlu, Emery O. Sugasawara, Charles E. Vonderach, Dilip P. Vijay, Yogendra Ranade, Jeff Hall, Dwight Manning
  • Method and apparatus for avoiding dicing chip-outs in integrated circuit die
    Publication number: 20060160269
    Abstract: A method and apparatus for avoiding dicing chip-outs in integrated circuit die comprises: (a) providing a wafer for forming a plurality of integrated circuit die thereon; (b) forming the plurality of integrated circuit die on the wafer; and (c) forming a saw street between the integrated circuit die on the wafer to relieve cutting stress in the wafer when the integrated circuit die are separated by a dicing saw.
    Type: Application
    Filed: May 18, 2005
    Publication date: July 20, 2006
    Inventors: Parthasarathy Rajagopalan, Zafer Kutlu, Emery Sugasawara, Charles Vonderach, Dilip Vijay, Yogendra Ranade, Jeff Hall, Dwight Manning