Abstract: A method and apparatus for performing data error detection and correction is disclosed for multi-level logic and in particular, three-level trinary logic of levels 0, 1, 2. A source of trinary data supplies individual pieces of data (trits of 0, or 1, or 2) in multiple trit groups (trytes) to two separate check trit generators which generate unique check trits for each tryte input. The check trits from the two check trit generators are compared to form syndrome trits which are used to control an error detection function. For single errors per tryte a data correction function is activated to increment or decrement the incorrect data through a multiplexer. Multiple errors or no error conditions are indicated, but do not gate the data correction function.

Abstract: A method and apparatus for performing data error detection and correction is disclosed for multi-level logic and in particular, three-level trinary logic of levels 0, 1, 2. A source of trinary data supplies individual pieces of data (trits of 0, or 1, or 2) in multiple trit groups (trytes) to two separate check trit generators which generate unique check trits for each tryte input. The check trits from the two check trit generators are compared to form syndrome trits which are used to control an error detection function. For single errors per tryte a data correction function is activated to increment or decrement the incorrect data through a multiplexer. Multiple errors or no error conditions are indicated, but do not gate the data correction function.

Abstract: A communications interface for transferring data from a first binary logic circuit to a second binary logic circuit by using a trinary logic transmission channel. The first set of binary logic signals is converted into a first set of binary control signals which, in turn, control trinary drivers connected to the transmission channel. The trinary drivers drive the transmission channel to one of three discrete voltage levels as opposed to one of two levels in binary systems. Trinary receivers are located on the second binary logic circuit and are connected to the trinary transmission channel. The receivers produce a second set of binary control signals which are translated into a second set of binary logic signals for use by the second binary logic circuit.