Abstract: A process of forming complementary insulated gate field effect transistors includes forming first and second well regions of first and second conductivity types in a planar semiconductor layer so that the well regions have an impurity retrograde impurity distribution profile. An insulator layer is then selectively formed with a first relatively thick insulator portion and thin gate portions. The first and second gates are formed on the relatively thin portions of the insulator layer. Insulator spacers are formed so as to extend laterally from the gates and from the relatively thick insulator portion. First impurities are introduced using the first gate and spacers as a mask to form first source and drain regions. Second impurities of an opposite conductivity type are introduced using the second gate and spacers as a mask to form source and drain regions of a complementary device.

Abstract: A complementary insulated gate field effect transistor comprises a semiconductor body having an effectively planar surface, the semiconductor body containing complementary conductivity type wells in which complementary transistors are formed. A field insulator layer is selectively formed on the surface of the body, the field insulator layer being hardened against radiation. That portion of the planar surface of the body on which the field insulator layer is formed is not lower than respective surface portions on which first and second gate insulator layers of the complementary conductivity type transistors are formed. In addition to respective gates, and source and drain region pairs, the complementary transistors have insulative spacers which abut sidewalls of the first and second gates and the field insulator layer and extend over portions of the source and drain regions.

Abstract: An edge connector is formed along a sidewall edge of a relatively thin semiconductor wafer. The wafer contains a signal processing circuit to which the edge connector is to be electrically joined. For this purpose a region of material capable of being bonded with conductive material is formed in the wafer and a trench pattern is formed in a first surface of the wafer, so as to expose a sidewall portion of the doped region. The doped region is connected to signal processing circuitry within the wafer. A metallic layer is then electroplated onto the exposed sidewall portion of the doped region. A layer of polishing resistant material, such as silicon nitride, is formed in the trench and the wafer is inverted and wax-mounted face down on a support member such that the first surface of the wafer faces the support member. The wafer is then polished as to effect a thinning of the wafer down to a level which exposes the polishing resistant material in the trench pattern.

Abstract: A wafer processing technique separates an extremely thin wafer into a plurality of completed circuit-containing dice without having to directly handle the wafer. In one embodiment, a substrate is thinned by forming a trench pattern in its top surface, the trench depth being the intended thickness of the die. A polishing resistant material is then formed in the trench and planarized down to a topside passivating layer, which is patterned to expose surface test regions. After wafer-probe testing, the wafer is affixed face-down on a support handle by means of an adhesion material such as wax. The substrate is backside-lapped down to the stop material in the trench, leaving a thin wafer layer. After the trench material is removed. Individual dice are separated from the support handle by melting the wax. In a further embodiment, a thin wafer layer if formed on a buried oxide layer. After trench patterning and face-down wax-mounting, the support substrate is polished down to the buried insulator layer.

Abstract: The problem of unwanted residual polysilicon stringers along the sidewalls of a field oxide layer employed in direct moat wafer processing is avoided by a processing scheme in which the sidewalls of the aperture in the field oxide layer are initially tapered prior to formation of the polysilicon layer to be used for the gate electrode(s). Because of the graduated thickness of the sidewalls of the field oxide layer, the thickness of the polysilicon layer formed thereon is substantially uniform over the entirety of the substrate. As a result, during subsequent masking of the polysilicon layer to define the gate electrode(s), all unmasked portions of the polysilicon are completely etched, leaving no residual material (e.g. stringers) that could be a source of device contamination.

Abstract: The separation constraint between the respective junctions formed between the drain regions of the complementary transistors and the semiconductor material in which they are formed is obviated by a structure which permits the respective drain regions of the opposite conductivity type transistors to have a reduced (effecting to zero) mutual separation and, at the same time, prevent the depletion regions fomed between the junctions defined by these source regions and the semiconductor material in which they are formed from spreading into contact with one another and thereby shorting the transistors together. This objective is achieved by a structure in which the source regions of the respective P and N channel transistors are formed so as to directly abut against one another and to be contiguous with a layer of buried dielectric isolation therebeneath.

Abstract: On the surface of a semiconductor structure containing portions to be selectively connected to an interconnection pattern, a thin conductive, uniform base layer, which promotes the growth of an interconnect conductor, is desposited. To define the interconnect structure, a thick layer of insulation material is selectively formed on the surface of the base layer with openings in the insulation layer exposing portions of the base layer that are to be connected to the interconnect layer. Next, on the portions of the base layer that are exposed by the openings in the insulation layer, a layer of interconnect metal, such as tungsten or gold, that effectively blocks the implantation of the ions through it, is selectively deposited to fill the openings in the insulation layer upon and even with the top surface of the insulation layer, so that the insulation layer and deposited metal are effectively planarized.

Abstract: Adhesion of gold interconnects to silicon dioxide is achieved by forming, through chemical vapor deposition, or plasma enhanced chemical vapor deposition, an extremely thin film of titanium over the entirety of exposed surfaces of an integrated circuit structure on which the gold lines are disposed and over which a silicon dioxide layer is to be formed. This extremely thin film of titanium is then exposed to a flow of an oxidizer to convert the titanium to a film of (insulating) titanium oxide which, unlike gold, strongly adheres to silicon dioxide. Silicon dioxide is then deposited on the titanium oxide film. In the resulting multilayer interconnect structure, the insulator consists of a layer of silicon dioxide adhering to a thin adhesive layer of TiO.sub.x or SiOx-TiO.sub.y at those locations whereat no gold lines are formed, while, on the gold conductor lines, the insulator contains silicon dioxide formed on a thin adhesive layer of SiO.sub.y -TiO.sub.x atop a TiO.sub.y -TiAu interface.

Abstract: Adhesion of gold interconnects to silicon dioxide is achieved by forming, through chemical vapor deposition, or plasma enhanced chemical vapor deposition, an extremely thin film of titanium over the entirety of exposed surfaces of an integrated circuit structure on which the gold lines are disposed and over which a silicon dioxide layer is to be formed. This extremely thin film of titanium is then exposed to a flow of an oxidizer to convert the titanium to a film of (insulating) titanium oxide which, unlike gold, strongly adheres to silicon dioxide. Silicon dioxide is then deposited on the titanium oxide film. In the resulting multilayer interconnect structure, the insulator consists of a layer of silicon dioxide adhering to a thin adhesive layer of TiO.sub.x or SiOx--TiO.sub.y at those locations whereat no gold lines are formed, while, on the gold conductor lines, the insulator contains silicon dioxide formed on a thin adhesive layer of SiO.sub.y --TiO.sub.x atop a TiO.sub.y --TiAu interface.

Abstract: The problem of unwanted residual polysilicon stringers along the sidewalls of a field oxide layer employed in direct moat wafer processing is avoided by a processing scheme in which the sidewalls of the aperture in the field oxide layer are initially tapered prior to formation of the polysilicon layer to be used for the gate electrode(s). Because of the graduated thickness of the sidewalls of the field oxide layer, the thickness of the polysilicon layer formed thereon is substantially uniform over the entirety of the substrate. As a result, during subsequent masking of the polysilicon layer to define the gate electrode(s), all unmasked portions of the polysilicon are completely etched, leaving no residual material (e.g. stringers) that could be a source of device contamination.

Abstract: Formation of a metallic interconnect pattern in submicron geometry architectures, without the photoresist being lifted off the substrate and resulting in the deposited metal being electroplated therebeneath, is achieved by a combination of a toughened-skin photoresist and pulsed electroplating. For toughening the skin of the photoresist and thereby enhancing its ability to withstand encroachment of the electrodeposited metal, the photoresist layer is illuminated with ultraviolet radiation. After the UV-irradiated photoresist has been allowed to cool, the resulting structure is placed in an electroplating bath, with appropriate electrodes disposed in the bath and connected to a said layer on the wafer for the deposition of the interconnect metal. The electrode differential is pulsed to provide a low frequency plating current through which the conductor metal is plated onto the seed metal on the wafer, as defined by the pattern of the toughened photoresist.