Abstract: Apparatus and methods for amplifier linearization are disclosed. In certain embodiments, an RF amplifier includes an RF input terminal that receives an RF input signal, an RF output terminal that provides an RF output signal, a gallium nitride field-effect transistor (GaN FET) having a gate connected to the RF input terminal and a drain connected to the RF output terminal. The GaN FET amplifies the RF input signal. The RF amplifier further includes a gallium arsenide field-effect transistor (GaAs FET) having a gate connected to the RF input terminal and a drain connected to the RF output terminal. The GaAs FET is operable to linearize the GaN FET.

Abstract: Aspects of this disclosure relate to linearized radio frequency amplifiers. A radio frequency amplifier can include first and second field effect transistors configured to receive a radio frequency input signal and provide first and second intermediate amplified signals, respectively. The first field effect transistor can have a first source and a first drain electrically biased at a first drain bias voltage and the second field effect transistor can have a second source and a second drain electrically biased at a second drain bias voltage different from the first drain bias voltage. The radio frequency amplifier can be configured to generate a combined output signal comprising the first and second intermediate amplified signal.

Abstract: Aspects of this disclosure relate to linearized radio frequency amplifiers. A radio frequency amplifier can include first and second field effect transistors configured to receive a radio frequency input signal and provide first and second intermediate amplified signals, respectively. The first field effect transistor can have a first source and a first gate electrically biased at a first gate bias voltage and the second field effect transistor can have a second source and a second gate electrically biased at a second gate bias voltage different from the first gate bias voltage.

Abstract: Circuits, systems, and methods to compensate for non-linearities associated with a switching circuit are discussed herein. For example, a switch circuit can include a switch arm and a linearizer arm. The switch arm can have a first transistor connected between an input node and an output node. The switch arm can be configured to receive a radio-frequency signal. The linearizer arm can have a second transistor connected to at least one of a gate or a body of the first transistor. The linearizer arm can be configured to compensate a non-linearity effect generated by the switch arm.

Abstract: The present disclosure relates to a radio frequency circuit comprising a linearizer circuit. The linearizer circuit may comprise a first capacitor and a second capacitor arranged in parallel. The first capacitor may have a positive third order derivative of charge with respect to voltage. The second capacitor may have a negative third order derivative of charge with respect to voltage. Related radio frequency modules and wireless communication devices are also disclosed.

Abstract: The fabrication of field-effect transistor (FET) devices is described herein where the FET devices include one or more body contacts implemented between source, gate, drain (S/G/D) assemblies to improve the influence of a voltage applied at the body contact on the S/G/D assemblies. The FET devices can include source fingers and drain fingers interleaved with gate fingers. The source and drain fingers of a first S/G/D assembly can be electrically connected to the source and drain fingers of a second S/G/D assembly. The source fingers and the drain fingers can be arranged in alternating rows.

Abstract: Disclosed herein are switching or other active FET configurations that implement a branch design with one or more interior FETs of a main path coupled in parallel with one or more auxiliary FETs of an auxiliary path. Such designs include a circuit assembly for performing a switching function that includes a branch with a plurality of auxiliary FETs coupled in series and a main FET coupled in parallel with an interior FET of the plurality of auxiliary FETs. The body nodes of the FETs can be interconnected and/or connected to a body bias network. The body nodes of the FETs can be connected to body bias networks to enable individual body bias voltages to be used for individual or groups of FETs.

Abstract: Circuits, systems, and methods to compensate for non-linearities associated with a switching circuit are discussed herein. For example, a switch circuit can include a switch arm and a linearizer arm. The switch arm can have a first transistor connected between an input node and an output node. The switch arm can be configured to receive a radio-frequency signal. The linearizer arm can have a second transistor connected to at least one of a gate or a body of the first transistor. The linearizer arm can be configured to compensate a non-linearity effect generated by the switch arm.

Abstract: The present disclosure relates to a radio frequency circuit comprising a linearizer circuit. The linearizer circuit may comprise a first capacitor and a second capacitor arranged in parallel. The first capacitor may have a positive third order derivative of charge with respect to voltage. The second capacitor may have a negative third order derivative of charge with respect to voltage. Related radio frequency modules and wireless communication devices are also disclosed.

Abstract: Disclosed herein are switching or other active FET configurations that implement a branch design with one or more interior FETs of a main path coupled in parallel with one or more auxiliary FETs of an auxiliary path. Such designs include a circuit assembly for performing a switching function that includes a branch with a plurality of auxiliary FETs coupled in series and a main FET coupled in parallel with an interior FET of the plurality of auxiliary FETs. The body nodes of the FETs can be interconnected and/or connected to a body bias network. The body nodes of the FETs can be connected to body bias networks to enable individual body bias voltages to be used for individual or groups of FETs.

Abstract: Aspects of the disclosure include a method of biasing a power amplifier including applying a drain voltage to a drain of the power amplifier, determining, based on the drain voltage, a range of acceptable gate voltages to apply to the power amplifier, determining a first optimal gate voltage within the range of acceptable gate voltages, determining a second optimal gate voltage within the range of acceptable gate voltages, selecting one of the first optimal gate voltage or the second optimal gate voltage to apply to the power amplifier, and applying either the first optimal gate voltage or the second optimal gate voltage to the gate of the power amplifier.

Abstract: Examples of the disclosure include a power amplifier comprising an input to receive an input signal, an output to provide an amplified output signal, a gate voltage bias node to receive a gate voltage bias signal, a first amplifier device having a first gate connection coupled to the gate voltage bias node and configured to receive the gate voltage bias signal, and a second amplifier device having a second gate connection coupled to the gate voltage bias node and configured to receive the gate voltage bias signal.

Abstract: Disclosed herein are switching or other active FET configurations that implement a branch design with one or more interior FETs of a main path coupled in parallel with one or more auxiliary FETs of an auxiliary path. Such designs include a circuit assembly for performing a switching function that includes a branch with a plurality of auxiliary FETs coupled in series and a main FET coupled in parallel with an interior FET of the plurality of auxiliary FETs. The body nodes of the FETs can be interconnected and/or connected to a body bias network. The body nodes of the FETs can be connected to body bias networks to enable individual body bias voltages to be used for individual or groups of FETs.

Abstract: The fabrication of field-effect transistor (FET) devices is described herein where the FET devices include one or more body contacts implemented between source, gate, drain (S/G/D) assemblies to improve the influence of a voltage applied at the body contact on the S/G/D assemblies. The FET devices can include source fingers and drain fingers interleaved with gate fingers. The source and drain fingers of a first S/G/D assembly can be electrically connected to the source and drain fingers of a second S/G/D assembly. The source fingers and the drain fingers can be arranged in alternating rows.

Abstract: Disclosed herein are switching or other active FET configurations that implement a branch design with one or more interior FETs of a main path coupled in parallel with one or more auxiliary FETs of an auxiliary path. Such designs include a circuit assembly for performing a switching function that includes a branch with a plurality of auxiliary FETs coupled in series and a main FET coupled in parallel with an interior FET of the plurality of auxiliary FETs. The body nodes of the FETs can be interconnected and/or connected to a body bias network. The body nodes of the FETs can be connected to body bias networks to enable individual body bias voltages to be used for individual or groups of FETs.

Abstract: Disclosed is a field effect transistor integrated within an associated transistor area, the field effect transistor comprising transistor contacts having a contact configuration of interleaved contact fingers including outer drain contact fingers located at opposite edges of the transistor area.

Abstract: Apparatus and methods for amplifier linearization are disclosed. In certain embodiments, an RF amplifier includes an RF input terminal that receives an RF input signal, an RF output terminal that provides an RF output signal, a gallium nitride field-effect transistor (GaN FET) having a gate connected to the RF input terminal and a drain connected to the RF output terminal. The GaN FET amplifies the RF input signal. The RF amplifier further includes a gallium arsenide field-effect transistor (GaAs FET) having a gate connected to the RF input terminal and a drain connected to the RF output terminal. The GaAs FET is operable to linearize the GaN FET.

Abstract: Disclosed herein are switching or other active FET configurations that implement a branch design with one or more interior FETs of a main path coupled in parallel with one or more auxiliary FETs of an auxiliary path. Such designs include a circuit assembly for performing a switching function that includes a branch with a plurality of auxiliary FETs coupled in series and a main FET coupled in parallel with an interior FET of the plurality of auxiliary FETs. The body nodes of the FETs can be interconnected and/or connected to a body bias network. The body nodes of the FETs can be connected to body bias networks to enable individual body bias voltages to be used for individual or groups of FETs.

Abstract: The fabrication of field-effect transistor (FET) devices is described herein where the FET devices include one or more body contacts implemented between source, gate, drain (S/G/D) assemblies to improve the influence of a voltage applied at the body contact on the S/G/D assemblies. The FET devices can include source fingers and drain fingers interleaved with gate fingers. The source and drain fingers of a first S/G/D assembly can be electrically connected to the source and drain fingers of a second S/G/D assembly. The source fingers and the drain fingers can be arranged in alternating rows.

Abstract: The present disclosure relates to a radio frequency circuit comprising a linearizer circuit. The linearizer circuit may comprise a first capacitor and a second capacitor arranged in parallel. The first capacitor may have a positive third order derivative of charge with respect to voltage. The second capacitor may have a negative third order derivative of charge with respect to voltage. Related radio frequency modules and wireless communication devices are also disclosed.