Patents by Inventor Dylan Hand

Dylan Hand has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Timing violation resilient asynchronous template
    Patent number: 9875327
    Abstract: An asynchronous circuit may include a single-rail logic datapath; one or more error-detecting latches; a controller that controls the error-detecting latches; and delay lines. The controller and the delay lines may cooperate to communicate with one or more other controllers that the output of the controlled error-detecting latches may be valid prior to when the error-detecting latches indicate whether or not an error occurred.
    Type: Grant
    Filed: February 4, 2016
    Date of Patent: January 23, 2018
    Assignee: University of Southern California
    Inventors: Peter A. Beerel, Melvin Breuer, Benmao Cheng, Dylan Hand
  • Timing violation resilient asynchronous template
    Patent number: 9558309
    Abstract: An asynchronous circuit may include a single-rail logic datapath; one or more error-detecting latches; a controller that controls the error-detecting latches; and delay lines. The controller and the delay lines may cooperate to communicate with one or more other controllers that the output of the controlled error-detecting latches may be valid prior to when the error-detecting latches indicate whether or not an error occurred.
    Type: Grant
    Filed: May 1, 2015
    Date of Patent: January 31, 2017
    Assignee: UNIVERSITY OF SOUTHERN CALIFORNIA
    Inventors: Peter A. Beerel, Melvin Breuer, Benmao Cheng, Dylan Hand
  • TIMING VIOLATION RESILIENT ASYNCHRONOUS TEMPLATE
    Publication number: 20160154905
    Abstract: An asynchronous circuit may include a single-rail logic datapath; one or more error-detecting latches; a controller that controls the error-detecting latches; and delay lines. The controller and the delay lines may cooperate to communicate with one or more other controllers that the output of the controlled error-detecting latches may be valid prior to when the error-detecting latches indicate whether or not an error occurred.
    Type: Application
    Filed: February 4, 2016
    Publication date: June 2, 2016
    Applicant: UNIVERSITY OF SOUTHERN CALIFORNIA
    Inventors: Peter A. Beerel, Melvin Breuer, Benmao Cheng, Dylan Hand
  • TIMING VIOLATION RESILIENT ASYNCHRONOUS TEMPLATE
    Publication number: 20150326210
    Abstract: An asynchronous circuit may include a single-rail logic datapath; one or more error-detecting latches; a controller that controls the error-detecting latches; and delay lines. The controller and the delay lines may cooperate to communicate with one or more other controllers that the output of the controlled error-detecting latches may be valid prior to when the error-detecting latches indicate whether or not an error occurred.
    Type: Application
    Filed: May 1, 2015
    Publication date: November 12, 2015
    Applicant: UNIVERSITY OF SOUTHERN CALIFORNIA
    Inventors: Peter A. Beerel, Melvin Breuer, Benmao Cheng, Dylan Hand