Abstract: A hypoxic chamber system comprises a hypoxic chamber having: a housing, an internal receiving chamber formed within the housing, a lid operably connectable to the housing to seal the receiving chamber in a closed position, a first input and a second input in communication with the receiving chamber, and an oxygen sensor positioned in the receiving chamber; a first regulator valve operatively connected to the first input and an oxygen source; a second regulator valve operatively connected to the second input and a non-oxygen source; and a controller electrically connected to the first regulator valve, the second regulator valve, and the oxygen sensor.

Abstract: A method and structure for a wafer level package is provided, which utilizes a plurality of spacer walls on a semiconductor wafer or a transparent substrate, which has the ability to decide the position of the sealant. As a result, the dimension of a device is decided by the position of the sealant and the spacer walls, therefore, shrinking the distance between the photosensitive zone and the sealant will enhance the gross dies after performing a die sawing process to the whole semiconductor wafer. In addition, the semiconductor process decides the height of the spacer walls so that the yield will be improved due to the fact that a uniformity of the gap, which is between the semiconductor wafer and the transparent substrate, and the width of sealant, will be controlled.

Abstract: A frame attaching process is described. The frame attaching process is adapted for attaching a transparent substrate to an active area of a chip using a frame, wherein the active area of the chip has a functional area. In the frame attaching process, the frame can be formed on the attaching surface of the transparent substrate or on the active area of the chip. Then, the attaching surface of the transparent substrate is attached to the active area of the chip using the frame under a negative pressure. Finally, the frame is solidified. Therefore, in the frame attaching process, the possibility of frame cracking can be reduced and the yield of the frame attaching process can be improved.

Abstract: A frame attaching process is described. The frame attaching process is adapted for attaching a transparent substrate to an active area of a chip using a frame, wherein the active area of the chip has a functional area. In the frame attaching process, the frame can be formed on the attaching surface of the transparent substrate or on the active area of the chip. Then, the attaching surface of the transparent substrate is attached to the active area of the chip using the frame under a negative pressure. Finally, the frame is solidified. Therefore, in the frame attaching process, the possibility of frame cracking can be reduced and the yield of the frame attaching process can be improved.

Abstract: A method and structure for a wafer level package is provided, which utilizes a plurality of spacer walls on a semiconductor wafer or a transparent substrate, which has the ability to decide the position of the sealant. As a result, the dimension of a device is decided by the position of the sealant and the spacer walls, therefore, shrinking the distance between the photosensitive zone and the sealant will enhance the gross dies after performing a die sawing process to the whole semiconductor wafer. In addition, the semiconductor process decides the height of the spacer walls so that the yield will be improved due to the fact that a uniformity of the gap, which is between the semiconductor wafer and the transparent substrate, and the width of sealant, will be controlled.

Abstract: A method and structure for a wafer level package is provided, which utilizes a plurality of spacer walls on a semiconductor wafer or a transparent substrate, which has the ability to decide the position of the sealant. As a result, the dimension of a device is decided by the position of the sealant and the spacer walls, therefore, shrinking the distance between the photosensitive zone and the sealant will enhance the gross dies after performing a die sawing process to the whole semiconductor wafer. In addition, the semiconductor process decides the height of the spacer walls so that the yield will be improved due to the fact that a uniformity of the gap, which is between the semiconductor wafer and the transparent substrate, and the width of sealant, will be controlled.