Abstract: A processor is provided with a decoder, a memory connected to the decoder and an execution stage connected to the decoder. The decoder receives each instruction. Each time the decoder receives an instruction, if the instruction contains a symbolic reference, the decoder determines whether or not the symbolic reference has been resolved into a numeric operand. If the symbolic reference has been resolved into a numeric operand, the memory retrieves, from a numeric reference table, a numeric operand to which the symbolic reference has been resolved. The execution stage then executes the instruction on the retrieved numeric operand in place of the symbolic reference. If the symbolic reference has not been resolved into a numeric operand, then the execution stage searches a data object, which relates each symbolic reference to a memory slot in which a corresponding numeric operand is stored, for a numeric reference relating the symbolic reference to a corresponding numeric operand.

Abstract: Methods and systems are disclosed for exploring instruction-level parallelism in superscalar processors by renaming stack entries. In a first embodiment, the stack renaming is implemented in a parallel structure that renames the instructions in parallel. In a second embodiment, the stack renaming is implemented in a serial structure that renames the instructions serially. In a third embodiment, the stack renaming is implemented in a combined parallel-serial structure that renames the instruction partially in parallel and partially in series.

Abstract: A process is provided for determining the beginning and ending of each instruction of a variable length instruction. Data lines are stored in a first memory area which illustratively is an instruction cache. Each data line comprises a sequence of data words that are stored at sequential address in a main memory. The data lines contain multiple encoded variable length instructions that are contiguously stored in the main memory. Multiple indicators are stored in a second memory area, including one indicator associated with each data word of the data lines stored in the first memory area. Each indicator indicates whether or not its associated data word is the initial data word of a variable length instruction. A sequence of data words may be fetched from the cache. The fetched sequence of data words includes a starting data word and at least the number of data words in the longest permissible instruction. Plural indicators (i.e.

Abstract: An improved method and apparatus for buffering and issuing instructions for use with superscalar microprocessors are disclosed.