Patents by Inventor E CHEN

E CHEN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12354919
    Abstract: The embodiments of the disclosure provide a manufacturing method of a package circuit, including the following steps. A circuit structure including a plurality of conductive pads is formed. A liquid crystal layer is formed on the circuit structure. An inspection step is performed, and the inspection step includes determining the conductivity of the conductive pads according to the result of the rotation of a liquid crystal layer oriented with an electric field. In addition, the liquid crystal layer is removed.
    Type: Grant
    Filed: November 4, 2021
    Date of Patent: July 8, 2025
    Assignee: Innolux Corporation
    Inventors: Yeong-E Chen, Bi-Ly Lin, Kuang Chiang Huang, Yu Ting Liu
  • Publication number: 20250149523
    Abstract: An electronic device is provided. The electronic device includes a circuit structure layer, a package structure, and an electronic element. The package structure is disposed on the circuit structure layer. The electronic element is embedded in the package structure. A thickness of the package structure is greater than or equal to 1.5 times a thickness of the electronic element.
    Type: Application
    Filed: January 9, 2025
    Publication date: May 8, 2025
    Applicant: Innolux Corporation
    Inventor: Yeong-E Chen
  • Publication number: 20250140645
    Abstract: An electronic device including a circuit layer, an electronic element, a first flow-path structure and a fluid material is disclosed. The electronic element is disposed on the circuit layer and electrically connected to the circuit layer. The first flow-path structure includes a first flow path, and the electronic element is disposed in the first flow-path structure. The fluid material is disposed in the first flow path. The fluid material is used for performing heat exchange with the electronic element. The circuit layer includes an input hole and an output hole, and the fluid material enters the first flow path through the input hole and exits the first flow path through the output hole.
    Type: Application
    Filed: December 30, 2024
    Publication date: May 1, 2025
    Applicant: InnoLux Corporation
    Inventors: Chin-Lung TING, Chung-Kuang WEI, Cheng-Chi WANG, Yeong-E CHEN, Yi-Hung LIN
  • Publication number: 20250118605
    Abstract: An electronic device is provided and includes a first conductive structure, a second conductive structure, a third conductive structure, a first insulating layer, a second insulating layer, a conductive element, an electronic component, and a plurality of passive components. The first insulating layer is disposed between the first conductive structure and the second conductive structure, and the second insulating layer is disposed between the second conductive structure and the third conductive structure. The second conductive structure is electrically connected to the first conductive structure at a first position, and the third conductive structure is electrically connected to the second conductive structure at a second position, wherein a center point of the first position and a center point of the second position is misaligned along a normal direction of a surface of the first insulating layer.
    Type: Application
    Filed: December 16, 2024
    Publication date: April 10, 2025
    Applicant: InnoLux Corporation
    Inventors: Yeong-E CHEN, Kuang-Chiang HUANG, Yu-Ting LIU, Hi-Hung LIN, Cheng-En CHENG
  • Patent number: 12266646
    Abstract: An electronic device is provided. The electronic device includes a circuit structure layer, a package structure, and an electronic element. The circuit structure layer includes a circuit layer and a plurality of first conductive pads. The package structure is disposed on the circuit structure layer. The electronic element is embedded in the package structure. The electronic element is electrically connected to the circuit layer through the plurality of first conductive pads. A thickness of the package structure is greater than or equal to 1.5 times a thickness of the electronic element.
    Type: Grant
    Filed: May 17, 2023
    Date of Patent: April 1, 2025
    Assignee: Innolux Corporation
    Inventor: Yeong-E Chen
  • Patent number: 12261127
    Abstract: A packaged semiconductor module comprises a substrate having a ground plane, an electronic device mounted on a surface of the substrate, a bond pad disposed on the surface of the substrate and electrically connected to the ground plane, a mold compound covering the electronic device, a conductive post disposed on a side of the electronic device, the conductive post extending from the bond pad and at least partially through the mold compound, and a conductive layer disposed on the mold compound and electrically coupled to the conductive post and to the ground plane, the conductive post, the conductive layer, and the ground plane together forming the integrated electromagnetic interference shield, the conductive post extending from the bond pad to the conductive layer in a direction perpendicular to a plane defined by the surface of the substrate.
    Type: Grant
    Filed: March 22, 2022
    Date of Patent: March 25, 2025
    Assignee: SKYWORKS SOLUTIONS, INC.
    Inventors: Anthony James LoBianco, Hoang Mong Nguyen, Matthew Sean Read, Howard E. Chen, Ki Wook Lee, Yi Liu
  • Publication number: 20250089154
    Abstract: Devices and methods related to metallization of ceramic substrates for shielding applications. In some embodiments, a ceramic assembly includes a plurality of layers, the assembly including a boundary between a first region and a second region, the assembly further including a selected layer having a plurality of conductive features along the boundary, each conductive feature extending into the first region and the second region such that when the first region and the second region are separated to form their respective side walls, each side wall includes exposed portions of the conductive features capable of forming electrical connection with a conductive shielding layer.
    Type: Application
    Filed: July 31, 2024
    Publication date: March 13, 2025
    Inventors: Shaul BRANCHEVSKY, Howard E. CHEN, Anthony James LOBIANCO
  • Publication number: 20250054876
    Abstract: Signal isolation for module with ball grid array. In some embodiments, a packaged module can include a packaging substrate having an underside, and an arrangement of conductive features implemented on the underside of the packaging substrate to allow the packaged module to be capable of being mounted on a circuit board. The arrangement of conductive features can include a signal feature implemented at a first region and configured for passing of a signal, and one or more shielding features placed at a selected location relative to the signal feature to provide an enhanced isolation between the signal feature and a second region of the underside of the packaging substrate.
    Type: Application
    Filed: July 5, 2024
    Publication date: February 13, 2025
    Inventors: Howard E. CHEN, David VIVEIROS, JR., Russ Alan REISNER, Robert Francis DARVEAUX
  • Patent number: 12224226
    Abstract: An electronic device is disclosed. The electronic device includes a circuit layer, an electronic element and a thermal conducting element. The electronic element is disposed on the circuit layer and electrically connected to the circuit layer. The thermal conducting element is disposed between the circuit layer and the electronic element. The thermal conducting element is used for performing heat exchange with the electronic element.
    Type: Grant
    Filed: August 29, 2022
    Date of Patent: February 11, 2025
    Assignee: InnoLux Corporation
    Inventors: Chin-Lung Ting, Chung-Kuang Wei, Cheng-Chi Wang, Yeong-E Chen, Yi-Hung Lin
  • Publication number: 20250046623
    Abstract: The application relates to a method for manufacturing an electronic device, and in particular, to a method for manufacturing an electronic device with a carrier substrate. The method includes: providing a carrier substrate; forming a first base layer on the carrier substrate; forming a working unit on the first base layer, performing a detection step on the working unit to identify whether a defect is present, wherein the detection step includes automated optical inspection (AOI), electrical detection, or a combination thereof; and repairing the electronic device.
    Type: Application
    Filed: October 18, 2024
    Publication date: February 6, 2025
    Inventors: Yeong-E CHEN, Cheng-En CHENG, Yu-Ting LIU, Cheng-Chi WANG
  • Publication number: 20250029907
    Abstract: A package device is provided and includes a redistribution layer. The redistribution layer includes a first dielectric layer, a conductive layer and a second dielectric layer, and the conductive layer is disposed between the first dielectric layer and the second dielectric layer. The redistribution layer has a test pattern including a conductive pattern, and the conductive pattern is formed of the conductive layer. The conductive pattern comprises a plurality of sub-portions arranged along at least one direction, and sizes of the plurality of sub-portions increase sequentially along the at least one direction.
    Type: Application
    Filed: October 8, 2024
    Publication date: January 23, 2025
    Applicant: InnoLux Corporation
    Inventors: Yeong-E CHEN, Cheng-En CHENG, Yu-Ting LIU
  • Publication number: 20250029910
    Abstract: An electronic component includes a first electronic unit including a plurality of pads, a first conductive layer, a second conductive layer, a first insulating layer having a first thickness, a second insulating layer having a second thickness, a second electronic unit, and a solder ball. The first conductive layer is disposed between the first electronic unit and the second conductive layer, and electrically connected to at least one of the pads through a conductive via. The first insulating layer is disposed between the first conductive layer and the second conductive layer. The second conductive layer is disposed between the first insulating layer and the second insulating layer. The first thickness is different from the second thickness. The second conductive layer is disposed between the first conductive layer and the second electronic unit. The second conductive layer is electrically connected to the second electronic unit through the solder ball.
    Type: Application
    Filed: October 8, 2024
    Publication date: January 23, 2025
    Applicant: Innolux Corporation
    Inventors: Yeong-E Chen, Yi-Hung Lin, Cheng-En Cheng, Wen-Hsiang Liao, Cheng-Chi Wang
  • Patent number: 12205854
    Abstract: The present disclosure provides an electronic device including a redistribution layer, a plurality of passive components, and an electronic component. The redistribution layer includes a first insulating layer, a second insulating layer, and a plurality of traces electrically connected to each other through a first opening of the first insulating layer and a second opening of the second insulating layer, wherein the first insulating layer has a first side away from the second insulating layer, and the second insulating layer has a second side away from the first insulating layer. The passive components are disposed on the first side. The electronic component is disposed on the second side. The plurality of passive components are electrically connected to the electronic component through the plurality of traces.
    Type: Grant
    Filed: September 19, 2023
    Date of Patent: January 21, 2025
    Assignee: InnoLux Corporation
    Inventors: Yeong-E Chen, Kuang-Chiang Huang, Yu-Ting Liu, Yi-Hung Lin, Cheng-En Cheng
  • Patent number: 12200857
    Abstract: The present disclosure provides a package device including a redistribution layer. The redistribution layer includes a first dielectric layer, a conductive layer, and a second dielectric layer, and the conductive layer is disposed between the first dielectric layer and the second dielectric layer, wherein the redistribution layer has a test mark, the test mark includes a conductive pattern formed of the conductive layer, the conductive pattern includes a center portion and a plurality of extension portions, and the plurality of extension portions are respectively connected to the center portion.
    Type: Grant
    Filed: September 27, 2023
    Date of Patent: January 14, 2025
    Assignee: InnoLux Corporation
    Inventors: Yeong-E Chen, Cheng-En Cheng, Yu-Ting Liu
  • Publication number: 20240430138
    Abstract: An apparatus for performing a fast common mode recharge is disclosed. The apparatus includes a transmitter circuit configured to transmit a differential signal on a communication bus that includes a true signal line and a complement signal line and a measurement circuit configured to measure respective voltage levels of the true signal line and the complement signal line. The apparatus further includes a control circuit configured to, in response to exiting a sleep mode, select one of a plurality of operation modes using the respective voltage levels of the true signal line and the complement signal line. The transmitter circuit is further configured to adjust the respective voltage levels of the true signal line and the complement signal line based on a selected operation mode of the plurality of operation modes.
    Type: Application
    Filed: June 21, 2023
    Publication date: December 26, 2024
    Inventors: Charles L. Wang, Yi-Hsiu E. Chen, Yu-Yau Guo, Wei-Ming Lee
  • Publication number: 20240405009
    Abstract: A dual-sided module can include a redistribution layer having first and second sides, and a first-side portion implemented on the first side of the redistribution layer and including a first component mounted on the first side of the redistribution layer, and a first mold structure implemented to at least partially encapsulate the first component. The dual-sided module can further include a second-side portion implemented on the second side of the redistribution layer and including a second component mounted on the second side of the redistribution layer, a plurality of conductive mounting structures, and a second mold structure implemented to at least partially encapsulate the second component. The second mold structure can further encapsulate the conductive mounting features while providing respective exposed mounting surfaces of the conductive mounting features.
    Type: Application
    Filed: May 25, 2024
    Publication date: December 5, 2024
    Inventors: Sundeep Nand NANGALIA, Howard E. CHEN, Anthony James LOBIANCO
  • Publication number: 20240389229
    Abstract: An electronic device includes a substrate, a first conductive structure, a second conductive structure, a first wire, and a second wire. The substrate includes a peripheral region. The first conductive structure is in the peripheral region and includes a first conductive layer and a second conductive layer. The first and the second conductive layer are arranged along a first direction. The second conductive structure is in the peripheral region and includes a third conductive layer. The first and the second conductive structure are arranged along a second direction, which is perpendicular to the first direction. The first wire is in the peripheral region and is electrically connected between the first and the third conductive layer. The second wire is in the peripheral region and is electrically connected to the second conductive layer. The first wire is adjacent to the second wire along the first direction.
    Type: Application
    Filed: July 29, 2024
    Publication date: November 21, 2024
    Inventors: Yu-Ting LIU, Yeong-E CHEN, Chean KEE
  • Patent number: 12148686
    Abstract: The present disclosure provides a package device and a manufacturing method thereof. The package device includes a redistribution layer which includes a first dielectric layer, a conductive layer and a second dielectric layer. The conductive layer is disposed between the first dielectric layer and the second dielectric layer. The redistribution layer has a test pattern that includes a first conductive pattern, and the first conductive pattern is formed of the conductive layer.
    Type: Grant
    Filed: January 11, 2022
    Date of Patent: November 19, 2024
    Assignee: InnoLux Corporation
    Inventors: Yeong-E Chen, Cheng-En Cheng, Yu-Ting Liu
  • Patent number: 12148630
    Abstract: The application relates to a method for manufacturing an electronic device, and in particular, to a method for manufacturing an electronic device with a carrier substrate. The method includes: providing a carrier, forming a first base layer on the carrier; and forming working units on the first base layer. The working units are spaced apart from one another.
    Type: Grant
    Filed: October 22, 2021
    Date of Patent: November 19, 2024
    Assignee: INNOLUX CORPORATION
    Inventors: Yeong-E Chen, Cheng-En Cheng, Yu-Ting Liu, Cheng-Chi Wang
  • Patent number: 12148658
    Abstract: The present disclosure discloses a method for manufacturing an electronic device, including: setting a basic working area; a photoresist coating process; a development process; an etching process; an exposure process; a metal plating process; and a polishing process, wherein the photoresist coating process, the development process, the etching process, the exposure process, the metal plating process and the polishing process respectively have a maximum optimized process area, and a smallest one of the maximum optimized process areas is selected as the basic working area.
    Type: Grant
    Filed: December 5, 2022
    Date of Patent: November 19, 2024
    Assignee: InnoLux Corporation
    Inventors: Cheng-Chi Wang, Yeong-E Chen, Cheng-En Cheng