Abstract: A verification technique in which a client verifies a server includes the use of two different digital certificates—one certificate derived from and including the other certificate. One certificate is programmed into the server it is desired to verify. This certificate includes various values that are signed with a secure private key, which may be, for example, the private key of the manufacturer of the server or subsystem within the server. The second certificate is derived from and includes the first certificate. This latter certificate also includes one or more server identity values (e.g., IP address, domain name) and is signed by a second private key that is preferably different than the private key used to sign the first certificate. Both certificates must be verified successfully by a client before a secured communication is permitted to proceed.

Abstract: A processor of a system initiates memory read transactions on a bus and provides information regarding the speculative nature of the transaction. A bus device, such as a memory controller, then receives and processes the transaction, placing the request in a queue to be serviced in an order dependent upon the relative speculative nature of the request. In addition, the processor, upon receipt of an appropriate signal, cancels a speculative read that is no longer needed or upgrades a speculative read that has become non-speculative.

Abstract: An electronic device can automatically configure its communication capability depending on its location. The device preferably includes a location determination module which may comprise, for example, a GPS receiver. The location determination module provides a location value to a CPU which uses the location value to determine in which region of the world (e.g., a country) the device is located. Based on that determination, the device configures its communication capability to be compliant with the accepted communication protocols, carrier frequency, etc. of that region.

Abstract: A technique for generating a strong random number for use in a cryptographic security system for a processor-based device is provided. The technique is particularly useful for restoring a random number to memory after data in the memory has been lost due to, for example, loss of backup power. Bits comprising a random number are automatically and iteratively written to the memory when another authorized device or application program attempts to access the processor-based device. Further randomness also may be provided by masking in additional bits whenever main power is cycled to the processor-based device.

Abstract: A computer system includes various security measures to insure that semi-permanent operating programs, such a boot blocks and firmware, are updated properly. For example, the system may include a security switch that can enable a host computer to load a replacement program into another computer, such as an appliance server for example, if the other computer fails. Also, if a replacement program is being loaded over a network connection that fails, the loading can resume automatically after re-establishment of the network connection. In addition, certain programs, such as boot blocks, may be verified in an execution memory, such as RAM, and loaded into a more permanent storage memory, such as ROM, only if verified.

Abstract: For use with a computer system having an intelligent mass storage disk array subsystem, including a microprocessor controller, a method for the distribution of data within the disk array based upon logical commands issued by the computer system. The disk controller reads a logical command and translates the commands into multiple drive specific commands, including drive physical parameter information such as head, sector and cylinder selection. The calculation of these physical parameters is based upon a number of factors including the operating system installed in the computer system, the type of interleave scheme, if any, specified by the computer system configuration, and disk specific parameters. The physical drive requests are then placed in a queue and executed by the microprocessor controller.

Abstract: A computer system is implemented according to the invention when priority information is included with a bus transaction. Instead of processing bus transactions on a first-come-first-served basis, a computer peripheral device can make decisions about the relative importance of a transaction and process the most important ones first. The priority scheme can be based upon the priority of the process that generates the transaction or on any other scheme. Included in the invention is logic to ensure that transactions of low relative priority do not get completely ignored during periods of high activity.

Abstract: Improved techniques for monitoring behavioral data of components of a computer system are disclosed. The monitoring begins to monitor a component once a monitoring program recognizes the presence of the component within the computer system. Then, the monitoring program tracks behavioral data generated by the component. A user interacting with the monitoring program is thus able to monitor the operation of the component by analyzing the various behavioral data it receives from the component. In one embodiment, the component is a hardware resource and its driver sends events to the monitoring program, and the driver receives commands from the monitoring program.

Abstract: A computer system comprising at least one processor and associated cache memory, and a plurality of registers to keep track of the number of cache memory lines associated with each process thread running in the computer system. Each process thread is assigned to one of the plurality of registers of each level of cache that is being monitored. The number of cache memory lines associated with each process thread in a particular level of the cache is stored as a number value in the assigned register and will increment as more cache memory lines are used for the process thread and will decrement as less cache memory lines are used. The number value in the register is defined as the "process thread temperature." Larger number values indicate warmer process thread temperature and smaller number values indicate cooler process thread temperature. Process thread temperatures are relative and indicate the cache memory line usage by the process threads running in the computer system at a particular level of cache.

Abstract: For use with a computer system having an intelligent mass storage disk array subsystem, including a microprocessor controller, a method for the distribution of data within the disk array based upon logical commands issued by the computer system. The disk controller reads a logical command and translates the commands into multiple drive specific commands, including drive physical parameter information such as head, sector and cylinder selection. The calculation of these physical parameters is based upon a number of factors including the operating system installed in the computer system, the type of interleave scheme, if any, specified by the computer system configuration, and disk specific parameters. The physical drive requests are then placed in a queue and executed by the microprocessor controller.

Abstract: An apparatus and method for performing queued or posted disk read operations. The present invention determines the range of memory addresses to which data is to be transferred from a disk to memory and sets protection for this range of addresses. The present invention will issue a read complete signal upon issuing the read command and will prevent access to the range of memory addresses until the transfer of information from disk to memory is actually complete. Upon actual completion of the data transfer, the present invention will issue a read complete confirmation which will clear address range protection. The present invention may be implemented using special circuitry and a modified device drive to store the range protection addresses. Alternately, the method of the present invention may utilize paged memory techniques present within the microprocessor.

Abstract: For use with a computer system having an intelligent mass storage disk array subsystem, including a microprocessor controller, a method for the distribution of data within the disk array based upon logical commands issued by the computer system. The disk controller reads a logical command and translates the commands into multiple drive specific commands, including drive physical parameter information such as head, sector and cylinder selection. The calculation of these physical parameters is based upon a number of factors including the operating system installed in the computer system, the type of interleave scheme, if any, specified by the computer system configuration, and disk specific parameters. The physical drive requests are then placed in a queue and executed by the microprocessor controller.

Abstract: A method for managing disk operations for a computer having a disk array utilizing parity fault tolerant and recovery techniques. A disk READ request results in a copy of the data and its associated parity information being stored in a reserved memory cache. Subsequent WRITE requests to the same disk sectors result in the computer system checking to see if a valid copy of the old parity and data are present in the reserved memory area for the purposes of generating new parity information without having to read the old data and parity information from the disk array.

Abstract: For use with a computer system having an intelligent mass storage disk array subsystem, including a microprocessor controller, a method for the distribution of data within the disk array based upon logical commands issued by the computer system. The disk controller reads a logical command and translates the commands into multiple drive specific commands, including drive physical parameter information such as head, sector and cylinder selection. The calculation of these physical parameters is based upon a number of factors including the operating system installed in the computer system, the type of interleave scheme, if any, specified by the computer system configuration, and disk specific parameters. The physical drive requests are then placed in a queue and executed by the microprocessor controller.

Abstract: A method and apparatus for improving disk performance during partial stripe write operations in a computer system having a disk array subsystem utilizing parity fault tolerance technique. When a partial stripe write generation is begun, the method determines if the area or stripe where the write is to occur is unused space in the file system. If not, the partial stripe write operation is performed using a preceding read operation to read the current data and parity information from the disk as would normally be done. However, if the write area is unused space in the file system, then the contents of the data stripe do not need to be preserved. In this instance, the partial stripe write operation can be performed without any preceding read operations. By obviating the necessity of a preceding read operation, much of the performance penalty of doing a partial stripe write in the case where the rest of the data stripe does not need to be preserved is removed.

Abstract: An array of disk drives organized as a data storage system including n parity drives forming n parity chains where each parity drive maintains the parity bits of a different combination of data drives and each data drive is included in at least two parity chains, and where no two data drives are associated with the same combination of parity chains. The present ECC technique requires only n parity drives for up to 2.sup.n -n-1 data drives for a maximum total of 2.sup.n -1 disk drives. Each data drive is included in two or more parity chains and each parity chain is unique. The n parity drives are taken two at a time, then three at a time, and so on up to n at a time, each combination being unique, until all of the data drives are associated with parity chains. The ECC technique is implemented using a disk controller which is coupled to the array of disk drives and constantly maintains the parity information on the parity drives.

Abstract: A bus master interface command protocol for use with a computer system having an intelligent mass storage disk array subsystem, including a bus master and microprocessor controller. The command protocol permits the computer system to issue disk array commands to the controller at a logical level without having to issue disk specific commands. The disk array subsystem microprocessor controller reads the logical commands, translates the commands into smaller disk specific commands, and queues the disk specific commands for processing. Upon completion of the logical command, the bus master controller asserts control over the computer system bus and manages the transfer of data to or from the computer system memory. The management of the disk array subsystem and the transfer of data is effectively off-loaded from the system processor permitting more efficient use of the processor.

Abstract: A method for detecting the presence of a replacement disk in a fault tolerant, intelligent mass storage disk array subsystem having a microprocessor based controller in a personal computer system and rebuilding the replacement disk independent of the computer system processor. The method calls for the microprocessor controller to run a disk array check at system powerup or at specified intervals to detect the existence of a replacement drive. The microprocessor then builds a series of disk drive commands which attempt to read every sector on the replacement disk. The read commands will return a null data read, indicating that the sector must be restored. The microprocessor controller converts the replacement read commands for all sectors on the replacement disk to write-restore commands. The microprocessor executes the write commands and restores the data to the replacement drive.