Abstract: A method for managing a configuration of heterogeneous software artifacts uses a common central configuration representation. An artifact of an unknown type, from an initial software solution, is submitted to a solution configuration tool. The solution configuration tool sends a request to a solution architect for locations of configuration files within the artifact. For each artifact whose configuration file locations have been requested from the solution architect, the solution configuration tool determines if each corresponding configuration file is a property file or an Extensible Markup Language (XML) file. If the corresponding configuration file is an XML file, then the solution architect provides a first and second xPath for locating the names and values of the configuration parameters in the XML configuration file. The configuration file and configuration parameter locator information is then stored in a configuration locator file.

Abstract: A method for managing a configuration of heterogeneous software artifacts through a common central configuration representation includes adding a plurality of software artifacts from an initial software solution to a heterogeneous configuration tool. Using this heterogeneous configuration tool, artifact-level configuration parameters are extracted out of selected software artifacts by the heterogeneous configuration tool. The extracted artifact-level configuration parameters are then presented in a single representation. A subset of the presented extracted artifact-level configuration parameters is mapped to a set of solution-level parameters, which are then exposed in a subsequent software solution. Thereafter, parameters for one or more of the solution-level parameters, which are used by the subsequent software solution, are exposed. These parameters for the subsequent software solution are then mapped back to the artifact-level configuration parameters of the subsequent software solution.

Abstract: A method for managing a configuration of heterogeneous software artifacts uses a common central configuration representation. An artifact of an unknown type, from an initial software solution, is submitted to a solution configuration tool. The solution configuration tool sends a request to a solution architect for locations of configuration files within the artifact. For each artifact whose configuration file locations have been requested from the solution architect, the solution configuration tool determines if each corresponding configuration file is a property file or an Extensible Markup Language (XML) file. If the corresponding configuration file is an XML file, then the solution architect provides a first and second xPath for locating the names and values of the configuration parameters in the XML configuration file. The configuration file and configuration parameter locator information is then stored in a configuration locator file.

Abstract: A method for managing a configuration of heterogeneous software artifacts through a common central configuration representation includes adding a plurality of software artifacts from an initial software solution to a heterogeneous configuration tool. Using this heterogeneous configuration tool, artifact-level configuration parameters are extracted out of selected software artifacts by the heterogeneous configuration tool. The extracted artifact-level configuration parameters are then presented in a single representation. A subset of the presented extracted artifact-level configuration parameters is mapped to a set of solution-level parameters, which are then exposed in a subsequent software solution. Thereafter, parameters for one or more of the solution-level parameters, which are used by the subsequent software solution, are exposed. These parameters for the subsequent software solution are then mapped back to the artifact-level configuration parameters of the subsequent software solution.

Abstract: Methods and systems for hardening a clocked latch against single event effects are disclosed. A system includes a first three-input OR gate, a first NAND gate, a second three-input OR gate, and a second NAND gate. The first three-input OR gate receives as inputs a clock signal, a first signal, and a redundant first signal. An output of the first three-input OR gate is connected to an input of the first NAND gate. The second three-input OR gate receives as inputs the clock signal, a second signal, and a redundant second signal. An output of the second three-input OR gate is connected to an input of the second NAND gate. A first output signal of the first NAND gate is connected to another input of the second NAND gate and a second output signal of the second NAND gate is connected to another input of the first NAND gate.

Abstract: Methods, systems and computer program products are provided for providing transactional quality of service providing transaction service level information from an application requesting a data transmission transaction to a communication process executing on a data processing system. The transaction service level information is provided separate from the data for the data transmission transaction. A quality of service level associated with the data transmission transaction is determined based on the transaction service level information received from the application. Other embodiments also provide for establishing a quality of service level without reference to transaction data content while further embodiments provide for establishing a quality of service level for responses.

Abstract: A method for modeling a circuit layout to determine behavior responsive to a radiation event is set forth. The method includes identifying a first portion of the circuit layout that includes at least one body region of a MOS transistor in the circuit layout, the at least one region having a width substantially equal to that of the MOS transistor. A first model corresponding to the first portion of the circuit layout is selected. A second portion of the circuit layout that includes at least a first region within a drain of the MOS transistor in the circuit layout is identified and an appropriate second model corresponding to the second portion of the circuit layout is selected, wherein the at least one second model includes at least one parasitic bipolar transistor.

Abstract: A decision block is incorporated into a circuit design to provide hardening against single event upset and to store data. The decision block includes a storage element that stores data as long as inputs to the decision block remain constant. The decision block receives a first data input and second data input from redundant logic blocks or from logic blocks designed to provide complementary outputs. The decision block provides an output that is at a same logic level as the first data input if the two data inputs are at expected logic levels during normal operating conditions (i.e., no disturbances). The decision block provides an output that is at a same logic level as a previous output of the decision block if the two data inputs are not at expected logic levels during normal operating conditions.

Abstract: A system for communicating between integrated circuits is disclosed. The system includes a driver having an input and an output. In response to a logic transition from a first logic state to a second logic state at the driver input, the driver output transitions from a low-power condition, to a transmitting condition, to the low-power condition. The system also includes a receiver having an input and an output. The receiver detects the logic state of the transmitting condition at the driver output and latches it to the receiver output after the driver output returns to the low-power condition. The system also includes a transmission line, which connects the driver output to the receiver input.

Abstract: A technique to read a stored state in a magnetoresistive random access memory (MRAM) device, such as a giant magneto-resistance (GMR) MRAM device or a tunneling magneto-resistance (TMR) device uses a bit line in an MRAM device that is segmented into a first portion and a second portion. An interface circuit compares the resistance of a first portion and a second portion of a first bit line to the resistance of a first portion and a second portion of a second bit line to determine the logical state of a cell in the first bit line. The interface circuit includes a reset circuit that selectively couples the outputs of the interface circuit together. A subsequent decoupling of the outputs allows cross-coupling within the interface circuit to latch the outputs to a logical state corresponding to the stored magnetic state, thereby allowing the stored state of a cell to be read.

Abstract: A compound polarization beam splitter (33) for use with a reflective, polarization-modulating, imaging device (10), e.g., a LCoS device, is provided. The compound PBS has: (a) an input prism (20); (b) an output prism (30), and (c) a polarizer (13), which is located between the two prisms (20,30) and which may be a wire grid polarizer (13a) or a multi-layer reflective polarizer (13b). Polarized illumination light (11) enters the input prism (20) through a first surface (21) and undergoes total internal reflection at a second surface (22) before being reflected from the polarizer (13) and polarization-modulated at the imaging device (10). The polarizer's tilt angle (?) is less than 45°, which reduces astigmatism and the required back working distance of the system's projection lens (74).

Abstract: Majority voting between triple redundant integrated circuits is used in order to provide an SEU hardened output signal. Accordingly, an input signal is processed in a predetermined manner to provide a first signal, the input signal is processed in the same manner to provide a second signal, and the input signal is also processed in the same manner to provide a third signal. A majority vote is taken between the first, second, and third signals by an SEU immune majority voter circuit, and an output signal is provided corresponding to the majority vote.

Abstract: A lens assembly adapted to be connected to a CRT and affixed to mounting structure in a projection television cabinet. The lens assembly includes a tubular lens mount having a longitudinal axis and at least a first optical lens element mounted along the longitudinal axis. A tubular focus mount extends along the longitudinal axis and fastening and locking structure connects the lens mount to the focus mount after a focus mount position is obtained. A CRT coupler is formed integrally with the focus mount and includes structure for securing a CRT and for securing the coupler to the mounting structure within the television cabinet. A second optical lens element is mounted to the CRT coupler. A flexible bladder may be used to contain coolant fluid between the CRT and the coupler. A flange may be provided to set a Scheimpflug angle between the CRT and the coupler.

Abstract: A technique to read a stored state in a magnetoresistive random access memory (MRAM) device, such as a giant magneto-resistance (GMR) MRAM device or a tunneling magneto-resistance (TMR) device uses a bit line in an MRAM device that is segmented into a first portion and a second portion. An interface circuit compares the resistance of a first portion and a second portion of a first bit line to the resistance of a first portion and a second portion of a second bit line to determine the logical state of a cell in the first bit line. The interface circuit includes a reset circuit that selectively couples the outputs of the interface circuit together. A subsequent decoupling of the outputs allows cross-coupling within the interface circuit to latch the outputs to a logical state corresponding to the stored magnetic state, thereby allowing the stored state of a cell to be read.

Abstract: A first cold spare circuit has first and second transistors, and a second cold spare circuit has third and fourth transistors. The first transistor has a gate controlled by a function of a first chip. A second transistor has its source and drain connected in series with the source and drain of the first transistor between the output and a first potential terminal. A third transistor has a gate controlled by a function of a second chip. A fourth transistor has its source and drain connected in series with the source and drain of the third transistor between the output and a second potential terminal. A first control circuit controls the gate of the second transistor and a second control circuit controls the gate of the fourth transistor so as to turn on one of the second and fourth transistors at a time.

Abstract: A technique to read a stored state in a magnetoresistive random access memory (MRAM) device, such as a giant magneto-resistance (GMR) MRAM device or a tunneling magneto-resistance (TMR) device uses a bit line in an MRAM device that is segmented into a first portion and a second portion. An interface circuit compares the resistance of a first portion and a second portion of a first bit line to the resistance of a first portion and a second portion of a second bit line to determine the logical state of a cell in the first bit line. The interface circuit includes a reset circuit that selectively couples the outputs of the interface circuit together. A subsequent decoupling of the outputs allows cross-coupling within the interface circuit to latch the outputs to a logical state corresponding to the stored magnetic state, thereby allowing the stored state of a cell to be read.

Abstract: Majority voting between triple redundant integrated circuits is used in order to provide an SEU hardened output signal. Accordingly, an input signal is processed in a predetermined manner to provide a first signal, the input signal is processed in the same manner to provide a second signal, and the input signal is also processed in the same manner to provide a third signal. A majority vote is taken between the first, second, and third signals by an SEU immune majority voter circuit, and an output signal is provided corresponding to the majority vote.

Abstract: A threshold control circuit for CMOS transistors wherein the voltage on the body of an n-channel reference transistor is controlled with a feedback circuit to produce a positive voltage on the body and decrease the threshold of the reference transistor to a desired value and the voltage on the body of a p-channel reference transistor is controlled with a feedback circuit to produce a negative voltage on the body and decrease the threshold of the reference transistor to a desired value.