Patents by Inventor E. Henry Stevens

E. Henry Stevens has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5385634
    Abstract: In fabricating a contact window to source/drain electrode next to a gate electrode of an integrated circuit: (1) establishing a structure with a window over the source/drain region next to the gate electrode; (2) establishing a region of titanium silicide over the source/drain electrode and establishing a titanium nitride layer over the window and gate electrode; (3) establishing a layer of silicon nitride over the titanium nitride layer; (4) patterning the silicon nitride layer; (5) using the patterned silicon nitride layer as a mask to pattern the titanium nitride layer; (6) adding another silicon nitride layer to seal the gate electrode where it is not protected by titanium nitride; (7) opening a window over the electrode by an anisotropic etch; (8) widening the window with an isotropic etch, using the silicon nitride and titanium nitride as a protective barrier; and (9) adding contact material in said windows.
    Type: Grant
    Filed: April 7, 1993
    Date of Patent: January 31, 1995
    Assignees: Ramtron International Corporation, Nippon Steel Semiconductor Corporation
    Inventors: Douglas Butler, E. Henry Stevens, Richard A. Bailey, Thomas C. Taylor
  • Patent number: 5170242
    Abstract: A reaction barrier is formed at an interface region between adjacent layers of a multilayer composite integrated circuit by implanting one or more active ionic species at energies effective to place the ionic species at or near the interface. A further step may include annealing the structure formed above to promote efficacy of the reaction barrier.
    Type: Grant
    Filed: May 10, 1991
    Date of Patent: December 8, 1992
    Assignees: Ramtron Corporation, NMB Semiconductor Company, Ltd.
    Inventors: E. Henry Stevens, Masahiro Maekawa
  • Patent number: 5070036
    Abstract: An improved structure and process for contacting and interconnecting semiconductor devices within a VLSI integrated circuit are described. The structure includes several regions which cooperate to provide (1) contacts of low electrical resistance to semiconductor device terminals, (2) barriers to unwanted metallurgic reactions, (3) strong bonds between major regions of the structure, (4) overall mechanical strength, (5) a primary current path of low electrical resistance, (6) a secondary current path in parallel with the primary current path, and (7) circuit bond pads for use in making electrical connections to the VLSI circuit. Because of the structure's mechanical strength, semiconductor devices may be placed beneath circuit bond pads. The inventive process facilitates accurate control of the composition and thickness of each of the several regions within the material structure.
    Type: Grant
    Filed: May 18, 1990
    Date of Patent: December 3, 1991
    Assignee: Quality Microcircuits Corporation
    Inventor: E. Henry Stevens
  • Patent number: 4977440
    Abstract: An improved structure and process for contacting and interconnecting semiconductor devices within a VLSI integrated circuit are described. The structure includes several regions which cooperate to provide (1) contacts of low electrical resistance to semiconductor device terminals, (2) barriers to unwanted metallurgic reactions, (3) strong bonds between major regions of the structure, (4) overall mechanical strength, (5) a primary current path of low electrical resistance, (6) a secondary current path in parallel with the primary current path, and (7) circuit bond pads for use in making electrical connections to the VLSI circuit. Because of the structure's mechanical strength, semiconductor devices may be placed beneath circuit bond pads. The inventive process facilitates accurate control of the composition and thickness of each of the several regions within the material structure.
    Type: Grant
    Filed: January 4, 1989
    Date of Patent: December 11, 1990
    Inventor: E. Henry Stevens
  • Patent number: 4784973
    Abstract: A titanium silicide/titanium nitride process is disclosed wherein the thickness of the titanium nitride can be regulated with respect to the titanium silicide. In particular, a control layer is formed in the contact opening during a reactive cycle to form a relatively thin (20 to 50 angstrom) control layer. Titanium is thereafter deposited and in another thermal reaction the control layer retards the development of titanium silicide without retarding the development of titanium nitride so that the thickness of titanium silicide is kept small. A double titanium process can also be used.
    Type: Grant
    Filed: August 24, 1987
    Date of Patent: November 15, 1988
    Assignee: INMOS Corporation
    Inventors: E. Henry Stevens, Paul J. McClure, Christopher W. Hill