Abstract: In a system comprising a plurality of digitally addressable electronic devices, all devices have the same construction and are designed for being connected in series to a common central monitoring station. The addressing of these devices is accomplished by a plurality of address lines which are connected to input contacts of the respective device. Within each device, a selection gate is connected to the input contacts which provides an enabling signal if the signal on said address lines has a predetermined bit pattern. Each device has output contacts connected to its input contacts to which the input contacts of a next device are connected. The address lines are connected from the input contacts to the output contacts of the device in such a way that the contacts are interchanged, and an inverter is inserted in one of said lines so that the bit pattern forming the address provided at the output contacts is different from the bit pattern received at the input contacts.