Abstract: The present disclosure provides a dynamic random access memory, which includes a storage diode and a control-FET. The storage diode is composed of a gate-floating FET, and two source/drains of the gate-floating FET serve as a cathode and an anode of the storage diode. The control FET is electrically connected to the cathode or the anode of the storage diode.

Abstract: The present disclosure provides a memory circuit, a memory device and an operating method of the memory device. The memory device includes a storage transistor, a variable capacitance device and a control transistor. The variable capacitance device is electrically connected to the gate of the storage transistor, and the control transistor is connected to the storage transistor in series.

Abstract: The present disclosure provides a memory device, which includes a plurality of electrically bipolar variable memory devices and a storage transistor. The electrically bipolar variable memory devices are electrically connected to a plurality of word lines respectively, the storage transistor is electrically connected to the electrically bipolar variable memory devices, where one end of each of the electrically bipolar variable memory devices is electrically connected to a corresponding one of the word lines, and another end of each of the electrically bipolar variable memory devices is electrically connected to the gate of the storage transistor.

Abstract: The present disclosure provides a memory circuit, a memory device and an operating method of the memory device. The memory device includes a storage transistor, a variable capacitance device and a control transistor. The variable capacitance device is electrically connected to the gate of the storage transistor, and the control transistor is connected to the storage transistor in series.

Abstract: The disclosure describes a tunneling field effect transistor having an overlapping structure between the source and drain regions providing a greater tunneling area. The source or drain region may be a doped region in a semi-conductive substrate. The other source or drain region may be formed by epitaxial deposition over the doped region. The gate is formed over the epitaxial region where the doped and epitaxial regions overlap. The doped region may be formed in a fin structure with the epitaxial region and gate being formed on the top and sides of the fin.

Abstract: The disclosure describes a tunneling field effect transistor having an overlapping structure between the source and drain regions providing a greater tunneling area. The source or drain region may be a doped region in a semi-conductive substrate. The other source or drain region may be formed by epitaxial deposition over the doped region. The gate is formed over the epitaxial region where the doped and epitaxial regions overlap. The doped region may be formed in a fin structure with the epitaxial region and gate being formed on the top and sides of the fin.

Abstract: The disclosure describes a tunneling field effect transistor having an overlapping structure between the source and drain regions providing a greater tunneling area. The source or drain region may be a doped region in a semi-conductive substrate. The other source or drain region may be formed by epitaxial deposition over the doped region. The gate is formed over the epitaxial region where the doped and epitaxial regions overlap. The doped region may be formed in a fin structure with the epitaxial region and gate being formed on the top and sides of the fin.

Abstract: The disclosure describes a tunneling field effect transistor having an overlapping structure between the source and drain regions providing a greater tunneling area. The source or drain region may be a doped region in a semi-conductive substrate. The other source or drain region may be formed by epitaxial deposition over the doped region. The gate is formed over the epitaxial region where the doped and epitaxial regions overlap. The doped region may be formed in a fin structure with the epitaxial region and gate being formed on the top and sides of the fin.

Abstract: A first memory unit includes a first bipolar-variable-resistance and a first control transistor. This first memory unit is configured to provide a function of a flash memory with first bipolar-variable-resistance transistor serving as a storage. In addition, a second bipolar-variable-resistance transistor and a second control transistor with the same structure as first memory unit can be used to serve as a second memory unit. An isolation transistor is connected between the first memory unit and the second memory unit. The isolation transistor can electrically isolate the first memory unit and the second memory unit from each other, thereby preventing sneak current from flowing between arrays among memory circuits.

Abstract: The disclosure describes a tunneling field effect transistor having an overlapping structure between the source and drain regions providing a greater tunneling area. The source or drain region may be a doped region in a semi-conductive substrate. The other source or drain region may be formed by epitaxial deposition over the doped region. The gate is formed over the epitaxial region where the doped and epitaxial regions overlap. The doped region may be formed in a fin structure with the epitaxial region and gate being formed on the top and sides of the fin.

Abstract: The disclosure describes a tunneling field effect transistor having an overlapping structure between the source and drain regions providing a greater tunneling area. The source or drain region may be a doped region in a semi-conductive substrate. The other source or drain region may be formed by epitaxial deposition over the doped region. The gate is formed over the epitaxial region where the doped and epitaxial regions overlap. The doped region may be formed in a fin structure with the epitaxial region and gate being formed on the top and sides of the fin.

Abstract: The disclosure describes a tunneling field effect transistor having an overlapping structure between the source and drain regions providing a greater tunneling area. The source or drain region may be a doped region in a semi-conductive substrate. The other source or drain region may be formed by epitaxial deposition over the doped region. The gate is formed over the epitaxial region where the doped and epitaxial regions overlap. The doped region may be formed in a fin structure with the epitaxial region and gate being formed on the top and sides of the fin.

Abstract: The disclosure describes a tunneling field effect transistor having an overlapping structure between the source and drain regions providing a greater tunneling area. The source or drain region may be a doped region in a semi-conductive substrate. The other source or drain region may be formed by epitaxial deposition over the doped region. The gate is formed over the epitaxial region where the doped and epitaxial regions overlap. The doped region may be formed in a fin structure with the epitaxial region and gate being formed on the top and sides of the fin.

Abstract: The disclosure describes a tunneling field effect transistor having an overlapping structure between the source and drain regions providing a greater tunneling area. The source or drain region may be a doped region in a semi-conductive substrate. The other source or drain region may be formed by epitaxial deposition over the doped region. The gate is formed over the epitaxial region where the doped and epitaxial regions overlap. The doped region may be formed in a fin structure with the epitaxial region and gate being formed on the top and sides of the fin.

Abstract: One time programming and repeatably random read integrated circuit memory has a storage device that programs the information by using dielectric-fuse mechanism. The main characteristics of dielectric fuse mechanisms is that by applying an electric field on the dielectrics, the ions or atoms in the dielectrics are drifted-out, or the dielectrics are burned-out, that create damage of the dielectric structure in a form of porosity, and the conductivity (resistivity) of tunneling current through the dielectrics changes the state from high conductivity (resistivity) to low conductivity (resistivity). The dielectric fuse mechanism has been integrated in VLSI circuits, completed the validation, and implemented by the fabrication of CMOS process.

Abstract: A first memory unit includes a first bipolar-variable-resistance and a first control transistor. This first memory unit is configured to provide a function of a flash memory with first bipolar-variable-resistance transistor serving as a storage. In addition, a second bipolar-variable-resistance transistor and a second control transistor with the same structure as first memory unit can be used to serve as a second memory unit. An isolation transistor is connected between the first memory unit and the second memory unit. The isolation transistor can electrically isolate the first memory unit and the second memory unit from each other, thereby preventing sneak current from flowing between arrays among memory circuits.

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a source structure at least partially in a semiconductor substrate. The semiconductor device structure also includes a channel structure over the semiconductor substrate. The source structure is partially covered by the channel structure. The semiconductor device structure further includes a drain structure covering the channel structure. The drain structure and the source structure have different conductivity types. A portion of the channel structure is sandwiched between the source structure and the drain structure. In addition, the semiconductor device structure includes a gate stack partially covering the channel structure.

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a source structure at least partially in a semiconductor substrate. The semiconductor device structure also includes a channel structure over the semiconductor substrate. The source structure is partially covered by the channel structure. The semiconductor device structure further includes a drain structure covering the channel structure. The drain structure and the source structure have different conductivity types. A portion of the channel structure is sandwiched between the source structure and the drain structure. In addition, the semiconductor device structure includes a gate stack partially covering the channel structure.

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a source structure in a semiconductor substrate. The semiconductor device structure also includes a channel layer over the semiconductor substrate. A first portion of the channel layer covers a portion of the source structure. A second portion of the channel layer laterally extends away from the source structure. The semiconductor device structure further includes a drain structure over the semiconductor substrate. The drain structure and the source structure have different conductivity types. The drain structure adjoins the second portion of the channel layer.

Abstract: This disclosure proposed one kind of one-time programming and repeatably random read integrated circuit memory. The storage device of this memory programs the information by using dielectric-fuse mechanism. The main characteristics of dielectric fuse mechanisms is that by applying an electric field on the dielectrics, the ions or atoms in the dielectrics are drifted-out, or the dielectrics are burned-out, that create damage of the dielectric structure in a form of porosity, and the conductivity (resistivity) of tunneling current through the dielectrics changes the state from high conductivity (resistivity) to low conductivity (resistivity). The dielectric fuse mechanism has been integrated in VLSI circuits, completed the validation, and implemented by the fabrication of CMOS process.