Abstract: An antenna device according to an example embodiment includes a silicon substrate of first type doping, at least two first doped regions formed by second type doping different from the first type doping, a second doped region formed by the second type doping outside a channel region surrounding the at least two first doped regions, and at least two gates disposed on a dielectric layer. In the antenna device, a resonant frequency is adjusted according to an external voltage individually applied to the at least two gates, and polarization information of a terahertz (THz) light source is obtained based on a pattern and an amount of an electric field measured at the at least two gates.

Abstract: A field-effect transistor for terahertz wave detection using a gate as an antenna includes a silicon substrate including a source and a drain formed outside a channel region surrounding the source, and a gate formed to be spaced apart from the silicon substrate and correspond to the channel region, on a dielectric layer formed on a surface of the silicon substrate, in which the drain has a width determined based on a first performance parameter associated with a terahertz wave reception rate of the field-effect transistor and the channel region has a width determined based on a second performance parameter associated with detection of a terahertz wave to be received by the field-effect transistor.

Abstract: An antenna device according to an example embodiment includes a silicon substrate of first type doping, at least two first doped regions formed by second type doping different from the first type doping, a second doped region formed by the second type doping outside a channel region surrounding the at least two first doped regions, and at least two gates disposed on a dielectric layer. In the antenna device, a resonant frequency is adjusted according to an external voltage individually applied to the at least two gates, and polarization information of a terahertz (THz) light source is obtained based on a pattern and an amount of an electric field measured at the at least two gates.

Abstract: A ternary logic circuit according to the present invention includes a pull-up device (100) and a pull-down device (200) connected in series between power voltage sources (VDD and GND), and an input voltage (VIN) source and output voltage (VOUT) source. When both the pull-up device (100) and the pull-down device (200) are turned off by an input voltage (VIN), both the pull-up device (100) and the pull-down device (200) operate as simple resistors which are affected only by an output voltage (VOUT) and form a ternary digit (“1” state) through voltage division. When only one of the pull-up device (100) or the pull-down device (200) is turned on to allow a current to flow therethrough, VDD (“2” state) or GND (“0” state) is output as the output voltage (VOUT). Accordingly, a bit density can be remarkably increased.

Abstract: A ternary logic circuit according to the present invention includes a pull-up device (100) and a pull-down device (200) connected in series between power voltage sources (VDD and GND), and an input voltage (VIN) source and output voltage (VOUT) source. When both the pull-up device (100) and the pull-down device (200) are turned off by an input voltage (VIN), both the pull-up device (100) and the pull-down device (200) operate as simple resistors which are affected only by an output voltage (VOUT) and form a ternary digit (“1” state) through voltage division. When only one of the pull-up device (100) or the pull-down device (200) is turned on to allow a current to flow therethrough, VDD (“2” state) or GND (“0” state) is output as the output voltage (VOUT). Accordingly, a bit density can be remarkably increased.