Abstract: In order to determine whether a reset function of an electronic device is safe, the states of a first checker and a second checker are toggled to preset states when a reset root is received from an external device. When a release of a local reset is received, whether the local reset was normally released is determined on the basis of a system clock. When the local reset is not normally released, the state of the second checker is toggled, and when the final local reset among the local resets is normally released, the state of the first checker is toggled. The release states of the local resets are monitored on the basis of the state of the first checker and the state of the second checker.

Abstract: A synchronization detector of a video signal processor includes a line buffer, a parameter extraction unit and synchronization detection unit. The line buffer sequentially stores a digital video signal corresponding to an input analog video signal, line by line of the input analog video signal. The parameter extraction unit continuously extracts horizontal synchronization parameters from the digital video signal stored line by line and continuously extracts vertical synchronization parameters from a portion of the digital video signal stored line by line. The synchronization detection unit generates horizontal and vertical synchronization signals of the input analog video signal using time information related to local minimum values of the horizontal synchronization parameters and time information related to local minimum values of the vertical synchronization parameters.

Abstract: A synchronization detecting apparatus includes a counter, an error detector, and a line length generator. The counter counts to a predetermined counter value in response to a clock signal. The error detector generates an error, which is the difference between a current counter value received from the counter and a previous line length, in response to a synchronization flag signal. The line length generator generates a current line length based on a compensated error and the predetermined counter value. The synchronization flag signal has an active level at a transitioning edge of a synchronization pulse signal contained in an input signal.

Abstract: A post-processing circuit for processing an image signal according to frequency components of an image signal includes: a low-frequency extracting unit outputting a low-frequency image component of the image signal as a low-frequency signal; a high-frequency extracting unit multiplying a high-frequency image component of the image signal by a first gain and outputting the multiplication product as a high-frequency signal; an intermediate-frequency extracting unit multiplying an intermediate-frequency image component of the image signal by a second gain and outputting the multiplication product as an intermediate-frequency signal; and an adder adding the low-frequency signal, the high-frequency signal, and the intermediate-frequency signal and outputting the addition sum as a post-processed signal, wherein the first gain and the second gain are differently set according to a pixel location in a spatial domain.

Abstract: A motion detection apparatus detecting motion in an image may include a black-and-white signal motion detector, a first color signal motion detector, a second color signal motion detector, and a final motion flag output unit. The motion detection apparatus may output a final motion flag in accordance with whether there is motion in a black-and-white image, whether there is first color motion in a color image, and whether there is second color motion in the color image. The motion detection apparatus may control a threshold value used to determine whether there is motion in an image in the present frame in response to accumulated information about whether there has been motion in the image for a predetermined past frame through to the previous frame.

Abstract: A motion detection apparatus detecting motion in an image may include a black-and-white signal motion detector, a first color signal motion detector, a second color signal motion detector, and a final motion flag output unit. The motion detection apparatus may output a final motion flag in accordance with whether there is motion in a black-and-white image, whether there is first color motion in a color image, and whether there is second color motion in the color image. The motion detection apparatus may control a threshold value used to determine whether there is motion in an image in the present frame in response to accumulated information about whether there has been motion in the image for a predetermined past frame through to the previous frame.

Abstract: A post-processing circuit for processing an image signal according to frequency components of an image signal includes: a low-frequency extracting unit outputting a low-frequency image component of the image signal as a low-frequency signal; a high-frequency extracting unit multiplying a high-frequency image component of the image signal by a first gain and outputting the multiplication product as a high-frequency signal; an intermediate-frequency extracting unit multiplying an intermediate-frequency image component of the image signal by a second gain and outputting the multiplication product as an intermediate-frequency signal; and an adder adding the low-frequency signal, the high-frequency signal, and the intermediate-frequency signal and outputting the addition sum as a post-processed signal, wherein the first gain and the second gain are differently set according to a pixel location in a spatial domain.

Abstract: A synchronization detector of a video signal processor includes a line buffer, a parameter extraction unit and synchronization detection unit. The line buffer sequentially stores a digital video signal corresponding to an input analog video signal, line by line of the input analog video signal. The parameter extraction unit continuously extracts horizontal synchronization parameters from the digital video signal stored line by line and continuously extracts vertical synchronization parameters from a portion of the digital video signal stored line by line. The synchronization detection unit generates horizontal and vertical synchronization signals of the input analog video signal using time information related to local minimum values of the horizontal synchronization parameters and time information related to local minimum values of the vertical synchronization parameters.

Abstract: A synchronization detecting apparatus includes a counter, an error detector, and a line length generator. The counter counts to a predetermined counter value in response to a clock signal. The error detector generates an error, which is the difference between a current counter value received from the counter and a previous line length, in response to a synchronization flag signal. The line length generator generates a current line length based on a compensated error and the predetermined counter value. The synchronization flag signal has an active level at a transitioning edge of a synchronization pulse signal contained in an input signal.