Patents by Inventor Eah Loon Alan Chuah

Eah Loon Alan Chuah has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • On-die termination (ODT) circuit configurable with via layer to support multiple standards
    Patent number: 11784118
    Abstract: An integrated circuit device with a single via layer, in which the via layer includes selectable via sites and/or jumpers. The selectable via sites and/or placement of jumpers may be used to configure and interconnect components and circuitry between distinct layers of multilayer circuits. In some implementations, selectively enabling via sites by filling via openings and/or using jumpers may implement a single-ended termination circuit with a first via configuration, a Thevenin termination circuit with a second via configuration, and/or a differential termination circuit with a third configuration.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: October 10, 2023
    Assignee: INTEL CORPORATION
    Inventors: Eah Loon Alan Chuah, Ting Ting Au
  • Via Configurable Edge-Combiner with Duty Cycle Correction
    Publication number: 20220014182
    Abstract: An integrated circuit device with a single via layer, in which the via layer includes selectable via sites and/or jumpers. The selectable via sites and/or placement of jumpers may be used to configure and interconnect components and circuitry between distinct layers of multilayer circuits. In some implementations, selectively enabling via sites by filling via openings and/or using jumpers may implement a data strobe generation circuit with a first via configuration and/or a data buffer circuit with a second configuration.
    Type: Application
    Filed: September 24, 2021
    Publication date: January 13, 2022
    Inventors: Chooi Pei Lim, Eah Loon Alan Chuah, Eng Huat LEE, Marian Serban, Marian Cretu
  • Configurable first in first out and deserializer circuitry
    Patent number: 10771063
    Abstract: An integrated circuit device with a single via layer, in which the via layer includes selectable via sites and/or jumpers. The selectable via sites and/or placement of jumpers may be used to configure and interconnect components and circuitry between distinct layers of multilayer circuits. In some implementations, selectively enabling via sites, such as by filling via opening and/or using jumpers, may form a deserializer circuit with a first via configuration or a first-in first-out (FIFO) circuit with a second via configuration.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: September 8, 2020
    Assignee: Intel Corporation
    Inventors: Eah Loon Alan Chuah, Hui Hui Ngu
  • ON-DIE TERMINATION (ODT) CIRCUIT CONFIGURABLE WITH VIA LAYER TO SUPPORT MULTIPLE STANDARDS
    Publication number: 20200126910
    Abstract: An integrated circuit device with a single via layer, in which the via layer includes selectable via sites and/or jumpers. The selectable via sites and/or placement of jumpers may be used to configure and interconnect components and circuitry between distinct layers of multilayer circuits. In some implementations, selectively enabling via sites by filling via openings and/or using jumpers may implement a single-ended termination circuit with a first via configuration, a Thevenin termination circuit with a second via configuration, and/or a differential termination circuit with a third configuration.
    Type: Application
    Filed: December 20, 2019
    Publication date: April 23, 2020
    Inventors: Eah Loon Alan Chuah, Ting Ting Au
  • Configurable First In First Out and Deserializer Circuitry
    Publication number: 20190319628
    Abstract: An integrated circuit device with a single via layer, in which the via layer includes selectable via sites and/or jumpers. The selectable via sites and/or placement of jumpers may be used to configure and interconnect components and circuitry between distinct layers of multilayer circuits. In some implementations, selectively enabling via sites, such as by filling via opening and/or using jumpers, may form a deserializer circuit with a first via configuration or a first-in first-out (FIFO) circuit with a second via configuration.
    Type: Application
    Filed: June 28, 2019
    Publication date: October 17, 2019
    Inventors: Eah Loon Alan Chuah, Hui Hui Ngu
  • Output Driver Circuit Configurable with Via Layer to Support Multiple Standards
    Publication number: 20190318991
    Abstract: An integrated circuit device with a single via layer, in which the via layer includes selectable via sites and/or jumpers. The selectable via sites and/or placement of jumpers may be used to configure and interconnect components and circuitry between distinct layers of multilayer circuits. In some implementations, selectively enabling via sites by filling via openings and/or using jumpers may implement a voltage-mode driver circuit with a first via configuration, a current-mode driver circuit with a second via configuration, and/or a differential driver circuit with a third configuration.
    Type: Application
    Filed: June 28, 2019
    Publication date: October 17, 2019
    Inventors: Eah Loon Alan Chuah, Ting Ting Au