Abstract: A data processing apparatus includes a SIMD (Single Instruction Multiple Data) array (10) of processing elements. The processing elements are operably divided into a plurality of processing blocks, the processing blocks being operable to process respective groups of data items.

Abstract: Incident support routing is described. The Internet is utilized to distribute the received customer support calls among a plurality of customer support agents who may be remotely located and geographically distributed. Voice data to voice-over-IP (VOIP) data packet conversion and VOIP to voice conversion may be utilized to facilitate a customer support call between a customer's telephone and a customer support agent's computer system.

Abstract: A data processing apparatus includes a plurality of processing elements arranged in a single instruction multiple data array. The apparatus includes an instruction controller operable to receive instructions from a plurality of instructions streams, and to transfer instructions from those instructions streams to the processing elements in the array, such that the data processing apparatus is operable to process a plurality of processing threads substantially in parallel with one another. A data transfer controller is provided which is operable to control transfer of data between the internal memory units associated with the processing elements, and memory external to the array.

Abstract: A method of scheduling instruction streams in a SIMD (single instruction multiple data) array of processing elements in which the processing elements are arranged in a plurality of SIMD processing blocks, comprises determining which instruction stream has priority at a particular moment in time, and transferring that determined instruction stream to the SIMD array.

Abstract: A parallel data processing apparatus using a SIMD array of processing elements is disclosed. The apparatus makes use of a register in order to control issuance of instructions to the processing elements in the array.

Abstract: A parallel data processing apparatus using a SIMD array of processing elements is disclosed. The apparatus makes use of a register in order to control issuance of instructions to the processing elements in the array.

Abstract: A method of processing data relating to geometrical primitives is disclosed. Each of the primitives has a plurality of vertices. The method uses a plurality of processing elements in parallel with one another, and comprises assigning respective vertex data to the processing elements, on each processing element, and in parallel with one another, performing at least one processing step on vertex data to produce processed vertex data, and transferring processed vertex data between processing elements so as to assemble primitive data.

Abstract: A data processing apparatus includes a plurality of processing elements arranged in a single instruction multiple data array.

Abstract: A data processing apparatus includes a plurality of processing elements arranged in a single instruction multiple data array. The apparatus includes at least one redundant processing element for processing data intended for a faulty processing element of the array.

Abstract: A data processing apparatus includes a plurality of processing elements arranged in a single instruction multiple data array for processing data relating to graphical primitives. Vertex data relating to graphical primitives is used as feedback data for the processing elements for additional processing.

Abstract: A data processing apparatus includes a plurality of processing elements arranged in a single instruction multiple data array for processing graphical data. A memory unit external to the array is utilised for storage of processed graphical data.

Abstract: A data processing apparatus includes a plurality of processing elements arranged in a single instruction multiple data array. The apparatus is operable to determine which of a plurality of instruction streams has priority at a particular moment in time, and to transfer that instruction stream to the SIMD array.

Abstract: A controller operable to control an array of processing elements comprises a retrieval unit operable to retrieve instruction items for each of a plurality of instructions streams, each instruction stream having a plurality of instructions items, a combining unit operable to combine the plurality of instruction streams into a serial instruction stream, and a distribution unit operable to distribute the serial instruction stream to an array of processing elements.

Abstract: A data processor comprises a plurality of processing elements arranged for parallel processing of data, and a controller for controlling the plurality of processing elements.

Abstract: A method for supplying instructions to a data processor having a plurality of processor arrays, each of which includes a plurality of processing elements, the method comprising retrieving instruction items for each of a plurality of instructions streams, each instruction stream having a plurality of instructions items, combining the plurality of instruction streams into a plurality of output instruction streams for supply to respective ones of the processor arrays, and distributing the output instruction streams to respective ones of the processor arrays.

Abstract: A controller for controlling a data processor having a plurality of processor arrays, each of which includes a plurality of processing elements, comprises a retrieval unit operable to retrieve a plurality of incoming instructions streams in parallel with one another, and a distribution unit operable to supply such incoming instruction streams to respective ones of the said plurality of processor arrays.

Abstract: A data processor comprises a plurality of processing elements arranged in a first plurality of SIMD (single instruction multiple data) processing arrays, and comprises a second plurality of controllers for transferring instructions to the processing arrays. Each controller is operable to transfer at least one instruction stream, and to transfer received instruction streams to at least one of the first plurality of processing arrays.

Abstract: A DPWM (1) has a delay lock loop (4) which receives an input clock signal and provides an out-of-phase delayed clock at the output of each of eight delay cells (35). A multiplexer (5) selects one of the delay cell outputs at any one time. This allows the DPWM (1) to have eight times the resolution which would otherwise be achieved with the same input clock. A programmable module (2) has a control block (20) which interfaces with external CPU and DSP hosts and transmits programmed parameters to finite state machine controllers (15), each providing an independent output.

Abstract: Two intelligent nodes are provided with the capability of negotiating a protocol between them so that if the intelligent nodes operate at two different protocols then they can select a protocol appropriate for their communication. Furthermore, the intelligent nodes are provided with a locking shift capability so as to select between codesets that are available within a selected protocol.

Abstract: A method of processing data relating to graphical primitives to be displayed on a display device using region-based SIMD multiprocessor architecture, has the shading and blending operations deferred until rasterization of the available graphical primitive data is completed.