Abstract: An integrated switching regulator device has a switching mode regulator comprising an input voltage source and a switching circuit coupled to the input voltage source configured to generate a pulsed voltage from the input voltage. A low pass filter is coupled to the switching regulator and is configured to filter the pulsed voltage to provide a regulated voltage to a load. The low pass filter comprises at least two LC stages, wherein the first LC stage comprises an air cored inductor and each subsequent LC stage comprises a non-air cored inductor. The switching circuit comprises two or more switching elements configurable to operate at a switching frequency of several megahertz.

Abstract: A switched mode power supply converter comprises a circuit pulse matching circuit configured to negate output voltage disturbance or noise during switching operation of a power conversion. The current pulse matching circuit input is driven by, or from, a power converter switch node of the switched mode power supply converter. The current pulse matching circuit comprises a rate-of-voltage change detection circuit driven by the power converter switch node.

Abstract: The invention provides a circuit in a switched mode power supply converter, and method of controlling a circuit. The circuit comprises a current pulse matching circuit configured to negate output voltage disturbance/noise during switching operation of a power conversion. The current pulse matching circuit input is driven by, or from, a power converter switch node of the switched mode power supply converter. The current pulse matching circuit comprises a rate-of-voltage change detection circuit driven by the power converter switch node.

Abstract: The invention describes an integrated switch mode power supply device comprising a switch mode regulator having a switching circuit coupled to an input voltage source to generate an output voltage from the input voltage and the switching circuit comprises at least two wide bandgap switches. An Nth order filter circuit is coupled to the switch mode regulator and configured to filter the output voltage to provide a supply voltage to a load, where N is greater than the integer two wherein the filter circuit comprises a LC or RC low pass filter comprising a plurality of LC or RC filter stages having a first filter stage and a last filter stage.

Abstract: The present invention provides an integrated switching regulator device which comprises a switching mode regulator comprising an input voltage source and a switching circuit coupled to the input voltage source to generate a pulsed voltage from the input voltage, and a low pass filter coupled to the switching regulator configured to filter the pulsed voltage to provide a regulated voltage to a load. The low pass filter comprises at least two LC stages, wherein the first LC stage comprises an air cored inductor and each subsequent LC stage comprises a non-air cored inductor. The switching circuit comprises two or more switching elements configurable to operate at a switching frequency of several MHz.

Abstract: The present disclosure is directed generally to switch mode power supplies operating in a master-slave configuration and provides a method of synchronizing the PWM outputs from the master and slave devices to avoid problems such, for example, as the generation of beat frequencies.

Abstract: The Application is directed at arrangements at which switch mode power converters share a common load. More particularly, the application provides a masterless arrangement in which no single converter controls the operation of the other converters. This is achieved by an arrangement in which each converter attempts to share its current measurement with other converters through an arbitration scheme employed on a data line, with the winning converter providing a defacto current measurement; for example, a maximum or minimum, to the overall arrangement.

Abstract: A DPWM (1) has a locked loop (4) which receives an input clock signal and provides an out-of-phase delayed clock at the output of each cell in the loop (35). A multiplexer (5) selects one of the cell outputs at any one time. This allows the DPWM (1) to have a greater resolution which would otherwise be achieved with the same input clock. The resolution is further increased using an interpolator. A programmable module (2) has a control block (20) which interfaces with external CPU and DSP hosts and transmits programmed parameters to finite state machine controllers (15), each providing an independent output.

Abstract: The Application is directed at arrangements at which switch mode power converters share a common load. More particularly, the application provides a masterless arrangement in which no single converter controls the operation of the other converters. This is achieved by an arrangement in which each converter attempts to share its current measurement with other converters through an arbitration scheme employed on a data line, with the winning converter providing a defacto current measurement; for example, a maximum or minimum, to the overall arrangement.

Abstract: The present disclosure is directed generally to switch mode power supplies operating in a master-slave configuration and provides a method of synchronizing the PWM outputs from the master and slave devices to avoid problems such, for example, as the generation of beat frequencies.

Abstract: A DPWM (1) has a locked loop (4) which receives an input clock signal and provides an out-of-phase delayed clock at the output of each cell in the loop (35). A multiplexer (5) selects one of the cell outputs at any one time. This allows the DPWM (1) to have a greater resolution which would otherwise be achieved with the same input clock. The resolution is further increased using an interpolator. A programmable module (2) has a control block (20) which interfaces with external CPU and DSP hosts and transmits programmed parameters to finite state machine controllers (15), each providing an independent output.

Abstract: A DPWM (1) has a delay lock loop (4) which receives an input clock signal and provides an out-of-phase delayed clock at the output of each of eight delay cells (35). A multiplexer (5) selects one of the delay cell outputs at any one time. This allows the DPWM (1) to have eight times the resolution which would otherwise be achieved with the same input clock. A programmable module (2) has a control block (20) which interfaces with external CPU and DSP hosts and transmits programmed parameters to finite state machine controllers (15), each providing an independent output.

Abstract: A DPWM (1) has a delay lock loop (4) which receives an input clock signal and provides an out-of-phase delayed clock at the output of each of eight delay cells (35). A multiplexer (5) selects one of the delay cell outputs at any one time. This allows the DPWM (1) to have eight times the resolution which would otherwise be achieved with the same input clock. A programmable module (2) has a control block (20) which interfaces with external CPU and DSP hosts and transmits programmed parameters to finite state machine controllers (15), each providing an independent output.

Abstract: A digital power controller (DPC, 1) controls an SMPC power stage (2). The DPC (1) interfaces with the SMPC power stage (2), and it has a system-on-a-chip (SoC) architecture including a digital signal processor (DSP, 5) for real-time control of SMPC outputs (such as output voltage) and a RISC processor (CPU, 6). An ADC (7) receives sense signals and routes them to the DSP (5), and a DPWM circuit (8) drives the SMPC. Communication with the CPU (6) is via a bus (10). The CPU (6) features include fault management and data transfers to the DSP co-processors and other peripheral blocks.

Abstract: A DPWM (1) has a delay lock loop (4) which receives an input clock signal and provides an out-of-phase delayed clock at the output of each of eight delay cells (35). A multiplexer (5) selects one of the delay cell outputs at any one time. This allows the DPWM (1) to have eight times the resolution which would otherwise be achieved with the same input clock. A programmable module (2) has a control block (20) which interfaces with external CPU and DSP hosts and transmits programmed parameters to finite state machine controllers (15), each providing an independent output.

Abstract: A DPWM (1) has a delay lock loop (4) which receives an input clock signal and provides an out-of-phase delayed clock at the output of each of eight delay cells (35). A multiplexer (5) selects one of the delay cell outputs at any one time. This allows the DPWM (1) to have eight times the resolution which would otherwise be achieved with the same input clock. A programmable module (2) has a control block (20) which interfaces with external CPU and DSP hosts and transmits programmed parameters to finite state machine controllers (15), each providing an independent output.