Abstract: The invention provides novel and improved methods that allow effective capture of valuable active ingredients in biomass such as whole stillage or thin stillage at cost-effective commercial scale. The invention also provides novel compositions of active ingredients with unique properties (e.g., nutritional values and enhanced bioavailability).

Abstract: The invention provides novel and improved methods that allow effective capture of valuable active ingredients in biomass (e.g., DDGS) at cost-effective commercial scale. The invention also provides novel compositions of active ingredients with unique properties (e.g., nutritional values and enhanced bioavailability).

Abstract: The invention is a novel scheme of performing an analog to digital conversion of simultaneous sampled analog inputs using multiple sample and hold circuits and a single successive approximation analog to digital converter (“SAR ADC”). Each of the analog inputs are stored on capacitors in the sample and hold circuits, and the sample and holds are sequentially connected to the capacitor DAC. After the digital conversion of the of the input signals stored on a sample and hold, the connected sample and hold is disconnected and the charge on the DAC is reset before the next sample and hold circuit is connected. The process is repeated until all analog inputs have been converted.

Abstract: The invention is a novel scheme of performing an analog to digital conversion of simultaneous sampled analog inputs using multiple sample and hold circuits and a single successive approximation analog to digital converter (“SAR ADC”). Each of the analog inputs are stored on capacitors in the sample and hold circuits, and the sample and holds are sequentially connected to the capacitor DAC. After the digital conversion of the of the input signals stored on a sample and hold, the connected sample and hold is disconnected and the charge on the DAC is reset before the next sample and hold circuit is connected. The process is repeated until all analog inputs have been converted.

Abstract: A switched-capacitor circuit for use in analog-to-digital conversion samples an input signal with respect to a reference voltage such that it significantly reduces a DAC settling time interval during each bit trial. In one exemplary embodiment, the switched-capacitor circuit having first and second groups of capacitor banks is coupled to a first input of a comparator and to a control circuit which provides control signals such that during a switching sequence, an equal value of capacitance is selected from each of the first and second groups of capacitor banks to reduce the DAC settling time interval, thereby improving the conversion rate.